I'm interested in designing an FMC card with 4 RX coherent channels for MIMO using two ADRV9009 chips. Are there are any design considerations for doing so? My team has done this with the AD9361 using the FMCOMMS5 as a basis. The axi_ad9361 core provided the l_clk output and clk input ports to control clocking between two chips and software handled the multichip synchronization procedure to phase lock the RX clocks. Is there an equivalent with the axi_adrv9009 core?
My current design approach is as follows:
- Keep util_adrv9009_xcvr to 4 RX channels (I'm not planning on using the RX_OS ports)
- Drive axi_adrv9009_rx_clkgen with rx_out_clk_0
- Drive adrv9009_core cores adc_clk with axi_adrv9009_rx_clkgen/clk_0
Here's a rough block diagram:
My questions for my clarification:
- Can we rely JESD synchronization to get coherent RX data? Assuming an AD9528 drives both chips and proper synchronization procedures.
- Should each ADRV9009 instead have its own instance of util_adxcvr and clocking?
- If so, how can the cores be internally synchronous in the FPGA