I'm interested in designing an FMC card with 4 RX coherent channels for MIMO using two ADRV9009 chips. Are there are any design considerations for doing so? My team has done this with the AD9361 using the FMCOMMS5 as a basis. The axi_ad9361 core provided the l_clk output and clk input ports to control clocking between two chips and software handled the multichip synchronization procedure to phase lock the RX clocks. Is there an equivalent with the axi_adrv9009 core? My current design approach is as follows:
Here's a rough block diagram:
My questions for my clarification:
We have under development a branch for a project that has two adrv9009's on the same board: https://github.com/analogdevicesinc/hdl/tree/prototype_som_2018_r2 .We are still working on software…
We have under development a branch for a project that has two adrv9009's on the same board: https://github.com/analogdevicesinc/hdl/tree/prototype_som_2018_r2 .We are still working on software, testing and validation, but this is the architecture that we think will work with our JESD204B Interface framework.
Your approach seems fine.
For sample level deterministic latency, the device clock (driving what currently is driven by axi_adrv9009_rx_clkgen/clk_0) should be generated along with sysref by the AD9528, and not by clockgen. We are using it because we only have a reference clock and may configure RX/TX/OBS with different rates and we don't have additional clocks from the AD9528 to FPGA. Depending on the FPGA you are using and the sampling rates, the device clock can be the same with the transceiver reference clock or it can be a different clock all together, being fed to the FPGA through a clock capable pin.
Maybe somebody from the https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/ forum can give additional pointers regarding getting coherent RX data from the chip.
On similar lines, we are working on a design that will have 4x adrv9009 for 8x coherent channels. Having a look at the prototype branch, at the moment that axi_adrv9009 core allows control allows for single or dual chips.
If we were to want to use 4 chips I guess we would need to expand this axi_adrv9009 IP to work with n channels effectively?
Do you have any plans to work on support for this yourself? I think that the proposed adrv9009-ZU11EG module would support adding an additional card for 4 chips in total?
We are planning to expand the support to N chips. ADRV9009-ZU11EG will ultimately support 4 chips in an FPGA design.
On the master branch we have created a new version of the ADRV9009 project, which uses a new approach on implementing the ADC/DAC and OBS paths, with our common JESD204 transport layer infrastructure. The prototype som will be ported to this approach, same for ADRV9009-ZU11EG.
Great thanks, I will have a look. Do you have any timescale for n chip support?
I think this month we should have the x2 with the generic IPs, but the implementation should be scalable to more. The x4 version will be available later, but depends on several variables and I cannot say for sure when we'll have it available and tested.