AD9361 HDL - Inserting a FFT into the block design


I am currently using the FMCOMMS3 with a VC707 carrier board and I have been able to implement and use HDL project in conjunction with the No-OS SW.  I have so far made changes to the No-OS SW and am beginning to get comfortable building my own applications here, however I would like to implement a FFT on the receive IQ samples and it seems that the best approach for this is to insert a FFT IP core into the HDL design.  Could you please advise me on the following:

1. I have attached a snip of the HDL block diagram (Image 1, unchanged from first build).  I have read in some related posts that the goal is to link the FFT block to the axi_dma, placing it before the DMA.  Could you please clarify what 'before' means?  In Image 2, which I have attached, should I connect the S_AXIS_S2MM (AXI_DMA) to the M_AXIS_DATA (FFT), circled in red?  To do this, I would have to delete the S_AXIS_S2MM connection (highlighted connection) which goes to the Ethernet block.  Should I connect the FFT S_AXIS_DATA to the Ethernet port?  Sorry if this seems obvious, I don't understand the block diagram or AXI interfaces well enough at the moment to know what I am doing.

2. I would ultimately still like to have access to the time domain samples so I am ultimately hoping that once the data is is captured from the ADC and stored into DDR, I can choose to read out and process with the FFT or simply send the time domain samples through my console as currently set up.  Should I actually be creating a new slave interface on AXI_MEM_INTERCONNECT  block and connecting the FFT to this?  If so, how would I wire the FFT to this?