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AD9361 HDL - Inserting a FFT into the block design


I am currently using the FMCOMMS3 with a VC707 carrier board and I have been able to implement and use HDL project in conjunction with the No-OS SW.  I have so far made changes to the No-OS SW and am beginning to get comfortable building my own applications here, however I would like to implement a FFT on the receive IQ samples and it seems that the best approach for this is to insert a FFT IP core into the HDL design.  Could you please advise me on the following:

1. I have attached a snip of the HDL block diagram (Image 1, unchanged from first build).  I have read in some related posts that the goal is to link the FFT block to the axi_dma, placing it before the DMA.  Could you please clarify what 'before' means?  In Image 2, which I have attached, should I connect the S_AXIS_S2MM (AXI_DMA) to the M_AXIS_DATA (FFT), circled in red?  To do this, I would have to delete the S_AXIS_S2MM connection (highlighted connection) which goes to the Ethernet block.  Should I connect the FFT S_AXIS_DATA to the Ethernet port?  Sorry if this seems obvious, I don't understand the block diagram or AXI interfaces well enough at the moment to know what I am doing.

2. I would ultimately still like to have access to the time domain samples so I am ultimately hoping that once the data is is captured from the ADC and stored into DDR, I can choose to read out and process with the FFT or simply send the time domain samples through my console as currently set up.  Should I actually be creating a new slave interface on AXI_MEM_INTERCONNECT  block and connecting the FFT to this?  If so, how would I wire the FFT to this?

  • On the current HDL release (2018_R1), data is passed as follows:

    AD9361 Interface -> FIFO -> DMA Controller -> Interconnect

    Technically you can put your IP anywhere, but the recommend place is here:

    AD9361 Interface -> FIFO -> NEW IP -> DMA Controller -> Interconnect back to PS.

    If you want to get both the pre and post FFT data just add another DMA+interconnect back to the PS for that additional datapath.


  • Thanks for the speedy response.  

    If I understand correctly, the data flow you mentioned is as shown in the attached image (highlighted lines) and the red circle is where I should be placing my New IP (In this case the FFT). 

    With regard to your second comment, what do you mean by PS (Processor?) ?  Also, when you refer to 'DMA + Interconnect', do you mean I should add another slave interface (i.e. S07_AXI) on the AXI_MEM_INTERCONNECT (Right most block in attached image) as well as another AXI_DMA_Controller for the Post FFT and hook it up in parallel to the AXI_AD9361_ADC_DMA controller?

    Thanks again for your help!

    EDIT/UPDATE: I have just attempted to place the FFT IP block in the position indicated by the red circle and it appears the output bus from the DMA controller is a 'Memory mapped AXI' whereas the FFT requires a streaming AXI type, it seems like it would make sense to add the FFT before the ADC_DMA_controller (for data interfacing simplicity), is this correct?

  • Your FFT should go before the DMA, after the FIFO.


  • Ok, thanks for clarifying. 

    Is there a recommended way to hook up the S_AXIS signals to the FIFO output? The data and Valid signals are OK, but I'm not sure how to connect the Sync (FIFO), data_tready(FFT) and data_tlast(FFT) signals. 

    Any suggestions?

  • Hi travisfcollins,

    I'm doing a similar project using the hdl_2016_r2 release. There's no FIFO between AD9361 interface and dma controller. Can you help to clarify why the FIFO is added in 2018_r1 release?

    Many thanks.

  • Hi, 

    I am using hdl_206_r2 as well and it does indeed have a FIFO, I've attached an image of the branch from my console.

    The FIFO can be seen in the block diagram as util_wfifo_v1.0 (please see attached image).



  • Hi Phil, 

    Sorry, I'm using 2015_r1 actually. After reading the release notes (, I believe that FIFO can be removed without any impact if you don't need data loopback function.


  • I would highly recommend using the current release. It can be hard for us to answer questions about older releases, especially if the tools associated with those releases have limited support from their vendors.

    In regards to the dataflow, you can put your DSP block before or after the pack blocks if you want, but know that there are 4 samples packed into the 64 bit output of the pack blocks, so your downstream processing must understand this interface. Data from the FIFO instead is clocked out at one sample at a time.

    in regards to your IP, I would recommend reading the documentation on that core so you understand what those interfaces do. How you configure them is really up to you.


  • So your recommendation is to upgrade from hdl_2016_r2 to hdl_2018_R1? I will do that. Thanks for that advice.  

    Regarding the implementation, I have read the documentation for the FFT(v9.0), util_cpack (AD core) and axi_ad9361(AD core) and from what I can tell, the FFT will assert waitstates on the S_TREADY line while processing data and requires the Master side (FIFO) to stop sending data at this time.  It doesn't look like util_cpack, util_wfifo or the axi_ad9361 have a signal which corresponds to processing that wait state.  

    Do you have any examples at all of how you might connect the S_AXIS_TREADY signal in this chain so that the FFT buffers do not get flooded with samples and begin to drop them?

    Also, the adc_sync signal on the FIFO side at the output of the packing function (util_cpack) indicates a sample of the first input channel, so this allows a downstream block (such as the FFT) to identify what are the correct I and Q samples.  the FFT does not appear to have a way of interpreting this either.

    Any potential reference designs with a succesful implementation or advice would be very helpful.   , have you had any luck with implementing a FFT core into your block design?  If so, I'm very keen to hear how you achieved it. 

    Best Regards,