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JESD stuck in reset w/ AD9208

Hi,

I am using the VCU108 Eval Board with an AD9208-3000EBZ Eval Board connected to HPC0. I am having trouble getting the JESD interface to come out of reset. Attaching debug probes to the relevant signals, I am finding that rx_reset from the JESD core is being held high (=1'b1) and so rx_reset_done from the JESD PHY is never asserted. I am using the J3 SMA connector on the AD9208-3000EBZ board to provide and create the rx_core_clk and rx_ref_clk as described in the ADI AD9208 git repo project. The debug cores will run successfully, which verifies that my clocks are active, and I have the clock provided on J3 set to the same frequency (using a signal generator) that the JESD IP states that the ref_clk should be. What else can cause this behavior?

Thanks,

Jacob



made title more relevant to question
[edited by: JacobC at 8:51 PM (GMT -4) on 12 Oct 2018]
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  • Thank you for those links. However, I am still having trouble understanding how to solve my problem. As the various links state, the REFCLK connections that would provide the clock I need directly to my FPGA transceivers via the AD9208-3000EBZ board were dropped in favor of routing GLBLCLK and SYSREF across the FMC. 

    The VCU108 board I am developing on does not have an SMA input that connects to the transceivers that I need (FMC HPC0), nor is there a user-programmable clock available (such as the SI570 that is available for the GTY transceivers). Is there a way for me to use the GLBLCLK input from the HPC0 and reroute that to the transceivers? Or, am I misunderstanding this entire operation?

  • Hello,

    I'll go over the VCU108 schematic and see if I can find a solution regarding this. I'll try to respond tomorrow.

    Regards,

    Adrian

  • Hello Jacob,

    First of all, given that we currently don't have support for the VCU108 nor AD9208 in our HDL/software repositories (the branch is a development branch), the below is theoretical, and you may encounter different problems when implementing.

    Looking over the VCU108 manual, it seems that BULLSEYE_GTH_REFCLK_C_P/N  reference clock goes to bank 228, which is adjacent to banks 227/226 of HPC1 and 229/230 of HPC0. According to Xilinx documentation, a reference clock for a transceiver bank can come from up to two banks above/below, meaning you could theoretically use BULLSEYE_GTH_REFCLK_C_P as a reference clock when connecting the board to either FMC0 or FMC1. This will be the reference clock for the transceivers (rx_ref_clk_p/n from the hdl repository).

    Hope this helps.

    Regards,

    Adrian

  • Adrian,

    Thank you for that. I somehow missed the Bullseye connector. However, I dont think that will work for us either as we don't have the capability to generate a differential clock externally, or the necessary Bullseye connector. I think we have decided on fabricating a simple adapter to insert between the AD9208 and the VCU108 that will allow us to drive the VCU108 transceivers will a regular external clock, as if the AD9208 J3 connector was driving it. As long as our PCB design follows the necessary rules, do you think that should work?

    Thanks,

    Jacob

  • I think most of the confusion is that AD9203 J3 provides the global clock ( device clock in JESD204 terms) and AD7-V2 J3 provides the transceiver reference clock to the evaluation design.

    If you can somehow take the AD9208 J3 clock and connect it to D4:D5 pins of the FMC (or B20:B21 for that matter), it may work, but I'm not sure how much your intermediary board degrades the clock quality...

    Another issue that should be checked is that for your FPGA, the reference clock and global clock are in the supported range.  I've used in the reference design a reference clock constraint of line rate / 20 = 750Mhz, but I think line rate /40 should work too. For the global clock, I've used line rate /40, as this is what we support with our JESD204B IP.

    Regards,

    Adrian

Reply
  • I think most of the confusion is that AD9203 J3 provides the global clock ( device clock in JESD204 terms) and AD7-V2 J3 provides the transceiver reference clock to the evaluation design.

    If you can somehow take the AD9208 J3 clock and connect it to D4:D5 pins of the FMC (or B20:B21 for that matter), it may work, but I'm not sure how much your intermediary board degrades the clock quality...

    Another issue that should be checked is that for your FPGA, the reference clock and global clock are in the supported range.  I've used in the reference design a reference clock constraint of line rate / 20 = 750Mhz, but I think line rate /40 should work too. For the global clock, I've used line rate /40, as this is what we support with our JESD204B IP.

    Regards,

    Adrian

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