I am using the VCU108 Eval Board with an AD9208-3000EBZ Eval Board connected to HPC0. I am having trouble getting the JESD interface to come out of reset. Attaching debug probes to the relevant signals, I am finding that rx_reset from the JESD core is being held high (=1'b1) and so rx_reset_done from the JESD PHY is never asserted. I am using the J3 SMA connector on the AD9208-3000EBZ board to provide and create the rx_core_clk and rx_ref_clk as described in the ADI AD9208 git repo project. The debug cores will run successfully, which verifies that my clocks are active, and I have the clock provided on J3 set to the same frequency (using a signal generator) that the JESD IP states that the ref_clk should be. What else can cause this behavior?
made title more relevant to question
[edited by: JacobC at 8:51 PM (GMT -4) on 12 Oct 2018]