DAQ2::what if pll2_vco_diff_m1 set to 2

Hi there,

I guess that I am not the first one to ask this question., what if pll2_vco_diff_m1 set to 2? ( We also tried setting it to 1. as a result, it breaks setup)

Here is what we have seen, setting it to 2 when in no OS example both ADC and DAC have 1Ghz sample rate, it still works and link clock appears to be 250mhz and correct.

As known, pll2_vco_diff_m1 is allowed to be 3,4,5. Having tried it set to 2, it is getting interesting.

when it is set to 3, master clock becomes 1Ghz. When it is set to 2, is master clock becoming 1.5Ghz or it is forced/ignored back down to 1Ghz?

It is useful for us if pll2_vco_diff_m1 set to 2 still is a valid setup?

Your comments are very appreciated!


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