According to schematic of AD9208-3000, reference clock into SMA connector J3 goes to to nets
Which then goes to a generic input of FPGA device (LA00_P_CC of HPC connector).
While this could provide JESD core clock, the PHY layer requires (FPGA carrier ZCU102) requires reflock goes to MGTREFCLK (FMC_HPC1_GBTCLK0_M2C_C_P).
Is there a way to use SMA J3 on ADC9208-3000 board to provide ref clock.
Below is my ref clock verilog code.
`timescale 1ns / 1ps
input wire refclk_pad_n,
input wire refclk_pad_p,
output wire refclk,
input wire gt_powergood,
//*********************************** Beginning of Code *******************************
// Static signal Assigments
assign tied_to_ground_i = 1'b0;
assign tied_to_vcc_i = 1'b1;
assign refclk = refclk_i;
assign coreclk = refclk_buf_i;
Hello, were you able to interface ad9208 with zcu102. I am also trying to interface both but could not find usable information for that. AD guys constantly say that zcu102 support will be available, not sure WHEN? If anyone has successfully implemented, please let met know
We've decided to support the dual AD9208 board as a reference design for the AD9208 ADC, as it doesn't require so many outside signals (different reference clocks and sysref) which influence the system and cannot be controlled when doing remote support.
The Dual AD9208 requires and FMC+ connector, so the ZCU102 cannot be used. We've created a project for VCU118. See https://wiki.analog.com/resources/eval/user-guides/ad9208_dual_ebz/ad9208_dual_ebz_hdl and https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad9208
There is a discussion here regarding how to use the single AD9208, but we won't support it further: https://ez.analog.com/linux-device-drivers/linux-software-drivers/f/q-a/108820/ad9208-on-zcu102-linux-problems/322475#322475
Hello Adrian, can you please let me know of J1 of 7044 to J55 of zcu102
We've used the PMOD PL connector from the ZCU102 to drive SPI signals to the HMC7044 evaluation board and configure it. If you don't have such a setup, the original devicetree should work fine (https://github.com/analogdevicesinc/linux/blob/ad9208-hmc7044/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9208.dts) , with just modifying the https://github.com/analogdevicesinc/linux/blob/ad9208-hmc7044/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9208.dts#L131 line to 3GHz.
We'll do additional tests tomorrow and post the progress
Hello Adran, we did some tests using our setup and correcting some of the things based on your setup. We were able to go up to 2.8GHz. We could not Sync JESD at 2.94912GHz. So we are now making setup exactly as yours. Can you please draw a rough sketch of how you are connecting J55 of ZCU102 to J1 of HMC7044. Because one is 12 pin connector and other is 22 pin connector. Just a rough sketch of pin connections between both connectors will help us. Also looking forward to your 3GHz test. Thanks.
I've tested with a lanerate of 15.36GBps and it worked fine on my end. I'm still working on cleaning things up, will probably take another day or so.
This commit message has been extended to include the pinout of the SPI: https://github.com/analogdevicesinc/linux/commit/91d7ec174d35eeb27bd6988e1541ea5368bd0564#diff-6d8c6a97994b7f4e8945cf8a797f4d4e
Can you please double check J1 to J55 connections as J1.10 is not connected to anywhere on HMC7044 board. Also Pin 16 and 18 are for SDATA one with 1.62k and other with 0 Ohm resistors. Also if you can kindly label each pin so that we are sure of SPI control signals.
The connections described in the commit message are correct: - J1.10 and J55.9 are connected both to GND on each board; - HMC7044 can be controlled via a three pins SPI (only one pin for the serial input/output data); however, a four pins SPI can be used by having that 1.62k resistor on the MOSI line - that way, short circuiting MOSI and MISO lines is avoided.
I've just found out that in the commit message all the J1 pins had an offset of 2. The connections should be: - EVAL-HMC7044 J28 -> AD9208-3000EBZ J201 - EVAL-HMC7044 J22 -> AD9208-3000EBZ J3 - EVAL-HMC7044 J38 -> ZCU102 J79 - EVAL-HMC7044 J39 -> ZCU102 J80 - EVAL-HMC7044 J1.20 -> ZCU102 J55.1 - EVAL-HMC7044 J1.18 -> ZCU102 J55.5 - EVAL-HMC7044 J1.16 -> ZCU102 J55.3 - EVAL-HMC7044 J1.14 -> ZCU102 J55.7 - EVAL-HMC7044 J1.12 -> ZCU102 J55.9
Sorry for the mistake.
No problem. I have already figured out and it is working. thanks.
On other note. Do you have any suggestion on clock scheme we will need if we use 2 AD9208-3000evaluation boards. I just need to understand general clock scheme, not any FPGA specific as we would develop our custom board.
If possible, you could rough sketch the clocks need to be provided to connectors. My intention is to clock them at 3GHz. I just want a general clock sketch not specific to ADS-V7.
Can you post this question on the High Speed ADCs forum ? They may be able to share a reference clocking scheme for a dual AD9208 setup.
We have an example of clocking scheme for another JESD204 project, https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg/hardware?rev=1557322291 . In that case each SOM has two JESD204 devices clocked from an HMC7044, with core clocks for both tx and rx and sysref for both tx and rx. The RX links / TX links are intended to work at the same rate and data is synchronized between devices. You can probably use that as a reference.
It's important that all devices in the system to have clocks generated from the same reference. If you want to support Subclass 1 deterministic latency, you'll need to provide a core clock and a source synchronous SYSREF signal. If the devices are always working together, it may be enough to have a single pair of core clock / sysref, but if you want independent links , you'll need a pair for each device. The core clocks need to be provided to a clock capable pin.
Depending on your FPGA and transceivers used, you'll need a number of reference clocks for the transceivers. For example, in ultrascale+ devices, the reference clock can be provided by a pin in the same bank or adjacent bank or adjacent bank +1, so by correctly selecting the banks used you can get away with a single reference clock. However, for best flexibility you may want to use an reference clock per device.
When we developed the ADRV9009-ZU11 board, it helped doing the FPGA baseline design in parallel with the hardware development to spot issues that are not evident from reading the documentation.
Okay thanks. I will post this question there. We have successfully initialized AD9208 up to 3GHz with ZCU102. We are still doing some verification checks to make sure we have achieved what we wanted to achieve. However, our final goal was to have 2 AD9208 evaluation board connected to 2 HPC FMC connectors. Since we are successful in using one, we are exploring to get 2nd integrated. However, there are only J79 and J80 available for HPC1 FMC connector which we have already used. There is no SMA connector available for HPC0 FMC connector. We had provided clocks as per your advice for single ad9208 evaluation card. If you have any advice, most welcome. By the way, we would also share our full experience on integrating AD9208 with zcu102 once we are done so that others can also take benefit. Thanks.