AD9208 Reference Clock from board SMA J3 issue


According to schematic of AD9208-3000, reference clock into SMA connector J3 goes to to nets


Which then goes to a generic input of FPGA device (LA00_P_CC of HPC connector). 

While this could provide JESD core clock, the PHY layer requires (FPGA carrier ZCU102) requires reflock goes to MGTREFCLK (FMC_HPC1_GBTCLK0_M2C_C_P).

Is there a way to use SMA J3 on ADC9208-3000 board to provide ref clock.

Below is my ref clock verilog code.  

`timescale 1ns / 1ps

module ad9208_clocking
  input  wire     refclk_pad_n,
  input  wire     refclk_pad_p,
  output wire     refclk,
  input  wire     gt_powergood,

  output          coreclk

//*********************************Wire Declarations**********************************
  wire            tied_to_ground_i;
  wire            tied_to_vcc_i;
  wire            refclk_i;
  wire            coreclk_i;

  wire            refclk_buf_i;
  wire            refclk_copy;

  //*********************************** Beginning of Code *******************************

  //  Static signal Assigments
  assign tied_to_ground_i    = 1'b0;
  assign tied_to_vcc_i       = 1'b1;

  IBUFDS_GTE4 ibufds_refclk0
    .O               (refclk_i),
    .ODIV2           (refclk_copy),
    .CEB             (tied_to_ground_i),
    .I               (refclk_pad_p),
    .IB              (refclk_pad_n)

  BUFG_GT refclk_bufg_gt_i
    .I       (refclk_copy),
    .CE      (gt_powergood),
    .CEMASK  (1'b1),
    .CLR     (1'b0),
    .CLRMASK (1'b1),
    .DIV     (3'b000),
    .O       (refclk_buf_i)

  assign refclk  = refclk_i;
  assign coreclk = refclk_buf_i;


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