Square wave output using fmcdaq2

Hi,

I'm confused, ad9144 is a high speed dac (1GSPS), why do you want it to output a squarewave of 1KHz?
The daq2 board has some filters on the output, you will have to change those to be able to transmit a sqare wave.

Take a look at https://ez.analog.com/fpga/f/q-a/81027/daq2-kcu105-send-data-to-dac

Are you familiar with our RF designs? If not, it may be of interest to you.

www.analog.com/en/products/adrv9008-2.html

www.analog.com/.../ad9361.html
wiki.analog.com/.../adrv936x_rfsom

Andrei

Thank you，Andrei

I am sorry for confusing you．I wanted to generate a square wave of 1 kHz because the modulator used operates by inputting a square wave of about 1 kHz to 2 kHz.

However, since the ADC/DAC I have is fmcdaq2, I would like to know haw to output a 1 kHz Square wave using fmcdaq2.

I'm sorry. I looked at https://ez.analog.com/fpga/f/q-a/81027/daq2-kcu105-send-data-to-dac and I saw the URL and could understand changing the filter of fmcdaq2, but I could not understand which part to change specifically.

Please tell me．

Yuta

Hi, Thank you for reply.

I understood what you were saying. Thank you．

I changed "sawtooth_wave" to "dac_dds_phase_0_0"  and changed "clk" to "dac_clk" in axi_9144_channel.v .

And then I ran make in /library/axi_ad 9144 and then executed make in /projects/daq2/vc707.

As a result, the build succeeded.

However, when executed with SDK, no UART message was displayed and a noise waveform was output.

Is it wrong to write mux?

  always @(posedge dac_clk) begin
    dac_enable <= (dac_data_sel_s == 4'h3) ? 1'b1 : 1'b0;
    case (dac_data_sel_s)
      4'h7: dac_data <= dac_pn15_data_s;
      4'h6: dac_data <= dac_pn7_data_s;
      4'h5: dac_data <= dac_pn15_data_i_s;
      4'h4: dac_data <= dac_pn7_data_i_s;
      4'h3: dac_data <= square_wave;
      4'h2: dac_data <= dma_data;
      4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
                          dac_pat_data_2_s, dac_pat_data_1_s};
      default: dac_data <= dac_dds_data;
    endcase
  end
  

Or is it because the value is not stored in "implement"? In that case, how can I give a value to "imlpement"?

please tell me.

Also, I need to change the DMA_buffer of github.com/.../fmcdaq2.c, right?

Hi,

What do you mean, no UART message?
Have you changed anything else? Can you try the reference design hdf to confirm the issue appears for your changes?

Andrei

Hi,

I already answer the above question, something went wrong and I can't see my message.

What do you mean, no UART message?
Have you changed anything else? Can you try the reference design hdf to confirm the issue appears for your changes?

"Also, I need to change the DMA_buffer of github.com/.../fmcdaq2.c, right?". Yes, you have to make sure you have selected the right path on the mux.

Have you used before the xsdb from xilinx?
you can connect to the PS7 and directly read and write registers after you initialize the system.

Andrei

HI, Thank you for reply.

I noticed that I made a mistake.The UART message was displayed properly. I'm sorry.

In order to select the right path on the mux, I changed "DAC_SRC_ZERO" of L123 to "DAC_SRC_SQUARE"  in /no-OS/common_drivers/dac_core/dac_core.h. And I changed L640 to L654 in /no-OS/fmcdaq2/fmcdaq2.c as follows.

#if DMA_BUFFER
	ad9144_channels[0].sel = DAC_SRC_SQUARE;
	ad9144_channels[1].sel = DAC_SRC_SQUARE;
	dac_data_setup(&ad9144_core);

	/*if(!dmac_start_transaction(ad9144_dma)) {
		printf("daq2: transmit data from memory\n");
	};*/
#else
	ad9144_channels[0].sel = DAC_SRC_DDS;
	ad9144_channels[1].sel = DAC_SRC_DDS;
	dac_data_setup(&ad9144_core);

	printf("daq2: setup and configuration is done\n");
#endif

Others have not changed both hdl and no-OS. (Except axi_ad 9144_channel.v)

Debugging was done, but 0 was output on the oscilloscope. What should I do?

I used xsdb. 

How can I connect to the PS7 and directly read and write registers?

Hi,

adc and dac core setup at 500MHz that is bad.
You have pn mismatch, This means your communication between FPGA and devices is not working.
Let's start with this. What sampling rates do you intend to use, lane rates?

Andrei

Hi, Thank you for your reply.

I understood that.

The sampling rate of the lane rate is as follows.

In the above example, I am using case 3.

switch (mode) {
		case '4':
			printf ("4 - ADC  600 MSPS; DAC  600 MSPS\n");
			p_ad9523_param->pll2_vco_diff_m1 = 5;
			(&p_ad9523_param->channels[DAC_FPGA_CLK])->
					channel_divider = 2;
			(&p_ad9523_param->channels[DAC_DEVICE_CLK])->
					channel_divider = 1;
			(&p_ad9523_param->channels[DAC_DEVICE_SYSREF])->
					channel_divider = 128;
			(&p_ad9523_param->channels[DAC_FPGA_SYSREF])->
					channel_divider = 128;
			(&p_ad9523_param->channels[ADC_FPGA_CLK])->
					channel_divider = 2;
			(&p_ad9523_param->channels[ADC_DEVICE_CLK])->
					channel_divider = 1;
			(&p_ad9523_param->channels[ADC_DEVICE_SYSREF])->
					channel_divider = 128;
			(&p_ad9523_param->channels[ADC_FPGA_SYSREF])->
					channel_divider = 128;
			p_ad9144_xcvr->reconfig_bypass = 0;
			p_ad9144_param->lane_rate_kbps = 6000000;
			p_ad9144_xcvr->lane_rate_kbps = 6000000;
			p_ad9144_xcvr->ref_clock_khz = 300000;
			p_ad9680_xcvr->reconfig_bypass = 0;
			p_ad9680_param->lane_rate_kbps = 6000000;
			p_ad9680_xcvr->lane_rate_kbps = 6000000;
			p_ad9680_xcvr->ref_clock_khz = 300000;
#ifdef XILINX
			p_ad9144_xcvr->dev.lpm_enable = 0;
			p_ad9144_xcvr->dev.qpll_enable = 0;
			p_ad9144_xcvr->dev.out_clk_sel = 4;

			p_ad9680_xcvr->dev.lpm_enable = 1;
			p_ad9680_xcvr->dev.qpll_enable = 0;
			p_ad9680_xcvr->dev.out_clk_sel = 4;
#endif
			break;
		case '3':
			printf ("3 - ADC  500 MSPS; DAC  500 MSPS\n");
			p_ad9523_param->pll2_vco_diff_m1 = 3;
			(&p_ad9523_param->channels[DAC_FPGA_CLK])->
					channel_divider = 4;
			(&p_ad9523_param->channels[DAC_DEVICE_CLK])->
					channel_divider = 2;
			(&p_ad9523_param->channels[DAC_DEVICE_SYSREF])->
					channel_divider = 256;
			(&p_ad9523_param->channels[DAC_FPGA_SYSREF])->
					channel_divider = 256;
			(&p_ad9523_param->channels[ADC_FPGA_CLK])->
					channel_divider = 4;
			(&p_ad9523_param->channels[ADC_DEVICE_CLK])->
					channel_divider = 2;
			(&p_ad9523_param->channels[ADC_DEVICE_SYSREF])->
					channel_divider = 256;
			(&p_ad9523_param->channels[ADC_FPGA_SYSREF])->
					channel_divider = 256;
			p_ad9144_xcvr->reconfig_bypass = 0;
			p_ad9144_param->lane_rate_kbps = 5000000;
			p_ad9144_xcvr->lane_rate_kbps = 5000000;
			p_ad9144_xcvr->ref_clock_khz = 250000;
			p_ad9680_xcvr->reconfig_bypass = 0;
			p_ad9680_param->lane_rate_kbps = 5000000;
			p_ad9680_xcvr->lane_rate_kbps = 5000000;
			p_ad9680_xcvr->ref_clock_khz = 250000;
#ifdef XILINX
			p_ad9144_xcvr->dev.lpm_enable = 1;
			p_ad9144_xcvr->dev.qpll_enable = 0;
			p_ad9144_xcvr->dev.out_clk_sel = 4;

			p_ad9680_xcvr->dev.lpm_enable = 1;
			p_ad9680_xcvr->dev.qpll_enable = 0;
			p_ad9680_xcvr->dev.out_clk_sel = 4;
#endif
			break;
		case '2':
			printf ("2 - ADC  500 MSPS; DAC 1000 MSPS\n");
			p_ad9523_param->pll2_vco_diff_m1 = 3;
			(&p_ad9523_param->channels[DAC_FPGA_CLK])->
					channel_divider = 2;
			(&p_ad9523_param->channels[DAC_DEVICE_CLK])->
					channel_divider = 1;
			(&p_ad9523_param->channels[DAC_DEVICE_SYSREF])->
					channel_divider = 128;
			(&p_ad9523_param->channels[DAC_FPGA_SYSREF])->
					channel_divider = 128;
			(&p_ad9523_param->channels[ADC_FPGA_CLK])->
					channel_divider = 4;
			(&p_ad9523_param->channels[ADC_DEVICE_CLK])->
					channel_divider = 2;
			(&p_ad9523_param->channels[ADC_DEVICE_SYSREF])->
					channel_divider = 256;
			(&p_ad9523_param->channels[ADC_FPGA_SYSREF])->
					channel_divider = 256;
			p_ad9144_xcvr->reconfig_bypass = 0;
			p_ad9144_param->lane_rate_kbps = 10000000;
			p_ad9144_xcvr->lane_rate_kbps = 10000000;
			p_ad9144_xcvr->ref_clock_khz = 500000;
			p_ad9680_xcvr->reconfig_bypass = 0;
			p_ad9680_param->lane_rate_kbps = 5000000;
			p_ad9680_xcvr->lane_rate_kbps = 5000000;
			p_ad9680_xcvr->ref_clock_khz = 250000;
#ifdef XILINX
			p_ad9144_xcvr->dev.lpm_enable = 0;
			p_ad9144_xcvr->dev.qpll_enable = 1;
			p_ad9144_xcvr->dev.out_clk_sel = 4;

			p_ad9680_xcvr->dev.lpm_enable = 1;
			p_ad9680_xcvr->dev.qpll_enable = 0;
			p_ad9680_xcvr->dev.out_clk_sel = 4;
#endif
			break;
		default:
			printf ("1 - ADC 1000 MSPS; DAC 1000 MSPS\n");
			p_ad9144_xcvr->ref_clock_khz = 500000;
			p_ad9680_xcvr->ref_clock_khz = 500000;
			break;
	}

Yuta

Hi,

The messages with SYSREF alignment  ERROR made me presume your link is down.
The setup is ok, sorry for the miss understanding. I forgot that the software takes into consideration the clock ratio. https://github.com/analogdevicesinc/no-OS/blob/master/common_drivers/adc_core/adc_core.c#L114

https://github.com/analogdevicesinc/hdl/blob/master/projects/daq2/common/daq2_bd.tcl#L143
https://wiki.analog.com/resources/fpga/docs/axi_ad9144


An example of how to use xsdb console

 

$ xsdb

****** Xilinx System Debugger (XSDB) v2017.4.1
  **** Build date : Jan 30 2018-15:42:35
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.


xsdb% connect
tcfchan#0
xsdb% target
  1  APU
     2  ARM Cortex-A9 MPCore #0 (Running)
     3  ARM Cortex-A9 MPCore #1 (Running)
  4  xc7z045
xsdb% target 2
xsdb% stop
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x113d0c (Suspended)
xsdb% mrd -force 0x44A00000 
44A00000:   DEADDEAD

xsdb% mrd -force 0x44A00000
44A00000:   DEADDEAD

xsdb% mrd -force 0x44A10000 
44A10000:   000A0062

xsdb% mrd -force 0x44A04418
44A04418:   00000000

xsdb% mwr -force 0x44A04418 0x3
xsdb% mrd -force 0x44A04418
44A04418:   00000003

xsdb% exit

Hi,

After programming to the FPGA, I tried using xdbd.
The results are shown below.

xsdb% connect                                                                   
tcfchan#0                                                                       
xsdb% target                                                                    
  1  xc7vx485t
     2  MicroBlaze Debug Module at USER2
        3  MicroBlaze #0 (Stop)
xsdb% target 3                                                                  
xsdb% mrd -force 0x44A00000                                                     
44A00000:   DEADDEAD

xsdb% mrd -force 0x44A10000                                                     
44A10000:   000A0062

xsdb% mrd -force 0x44A04418                                                     
44A04418:   00000000

xsdb% mwr -force 0x44A04418 0x3                                                 
xsdb% mrd -force 0x44A04418                                                     
44A04418:   00000003

xsdb% exit                                                                      
exit

After that I ran with SDK, but as before, PN mismatch occurred.

Available sampling rates:
	1 - ADC 1000 MSPS; DAC 1000 MSPS
	2 - ADC  500 MSPS; DAC 1000 MSPS
	3 - ADC  500 MSPS; DAC  500 MSPS
	4 - ADC  600 MSPS; DAC  600 MSPS
choose an option [default 1]:
3 - ADC  500 MSPS; DAC  500 MSPS

CPLL ENABLE

CPLL ENABLE
Tx link is enabled
Measured Link Clock: 125 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment ERROR
Rx link is enabled
Measured Link Clock: 125 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment ERROR
adc_setup adc core initialized (500 MHz).
dac_setup dac core initialized (500 MHz).
main ad9680 - PN9 sequence mismatch!
main ad9680 - PN23 sequence mismatch!
daq2: RX capture done.

No waveform was output at all．

After that, if you rewrite 0x44A04418 to 0x0 with xsbd, the sine waveform was output．

Yuta

Hi,

Any changes to hardware or clock/rates that you haven't mentioned?
I've seen in other threads problems caused by ILA's with no timing issue reported. Do you have ILA's in the system?
Better of can you start fresh on a new workspace hdl_2018_r1 and no-Os 2018_r1? Validate that the design is working, then add only the last discussed square wave generator in HDL.

Andrei

Hi,

Any changes to hardware or clock/rates that you haven't mentioned?
I've seen in other threads problems caused by ILA's with no timing issue reported. Do you have ILA's in the system?
Better of can you start fresh on a new workspace hdl_2018_r1 and no-Os 2018_r1? Validate that the design is working, then add only the last discussed square wave generator in HDL.

Andrei

Hi, thank you for your reply.

There is not any change in hardware or clock / rate that I do not mention.

There is no ILA in my system. Should I add ILA? Please tell me how to add if I should add ILA.

I will try to start with a new workspace hdl_2018_r1 and no-Os 2018_r1.

Yuta

Hi,

Don't add any ILA's.
Can you make a testbench and simulate the square wave generator?

Andrei

Hi,

I understood not adding ILA.
Since I have not made a test bench, I am not simulating a square wave generator.
I will try to create the test bench.

Yuta

Hi, 

I tried to start with a new workspace hdl_2018_r1 and no-Os 2018_r1.

As a result of the execution, no error appeared on the UART screen, but the waveform was still not output.

And I tried creating a test bench, but I could not make it well. How should I change it?

//square_wave.v


`timescale 1ns / 1ps

module square_wave(
CLK,
increment,
dout
);
input  CLK;
input [31:0]  increment;
reg  [15:0]  wave = 0;
reg  [15:0]  sawtooth_wave = 'd0;
output dout;

always @(posedge CLK)begin
  sawtooth_wave <= sawtooth_wave + increment;
  wave <= {16{sawtooth_wave[31]}};
end

square_wave i_square_wave(
CLK,
increment,
//wave,
//sawtooth_wave,
dout
);
endmodule

//square_wave_tb.v  //testbench

`timescale 1ns / 1ps
 

module square_wave_tb();
reg          CLK;
reg  [31:0]  increment;
reg  [15:0]  wave = 0;
reg  [15:0]  sawtooth_wave = 'd0;
wire dout;
square_wave i_square_wave(
.CLK (CLK),
.increment (increment),
.wave (wave),
.sawtooth_wave (sawtooth_wave),
.dout (dout)
);

always
  begin
    #50 CLK =~CLK;
  end
   
always @(posedge CLK)begin
  sawtooth_wave <= sawtooth_wave + increment;
  wave <= {16{sawtooth_wave[31]}};
end

endmodule

Yuta

Hi,

Use 16 bits for increment.
Fix sawtooth_wave[31], you only have 16 bits there.

Andrei

Hi, Thank you for your reply.

I had a lot of misunderstandings.
After changing the bit number to 16, I improved the testbench and it worked correctly.

I checked the NCO implemented in axi_ad 9144_channel.v on the test bench before, but square wave output was not obtained. Therefore I think that I failed even if I reworked the workspace.

I changed the increment to "16'd1" and simulated the test bench. As a result, it was confirmed that the square wave was outputted on the simulation.

Like the testbench, I added these to axi_ad 9144_channel.v, changed sawtooth_wave to dac_dds_phase_0_0, then built again, but the following error occurred.

*** Running vivado
    with args -log system_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_top.tcl -notrace


****** Vivado v2017.4.1 (64-bit)
  **** SW Build 2117270 on Tue Jan 30 15:31:13 MST 2018
  **** IP Build 2095745 on Tue Jan 30 17:13:15 MST 2018
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source system_top.tcl -notrace
Command: open_checkpoint /home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/system_top.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1159.902 ; gain = 0.000 ; free physical = 1330 ; free virtual = 4428
INFO: [Netlist 29-17] Analyzing 5575 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4.1
INFO: [Device 21-403] Loading part xc7vx485tffg1761-2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/.Xil/Vivado-22481-aoyagi-VirtualBox/dcp1/system_top_board.xdc]
Finished Parsing XDC File [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/.Xil/Vivado-22481-aoyagi-VirtualBox/dcp1/system_top_board.xdc]
Parsing XDC File [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/.Xil/Vivado-22481-aoyagi-VirtualBox/dcp1/system_top_early.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.srcs/sources_1/bd/system/ip/system_sys_mb_debug_0/system_sys_mb_debug_0.xdc:50]
get_clocks: Time (s): cpu = 00:00:18 ; elapsed = 00:00:40 . Memory (MB): peak = 2698.164 ; gain = 712.832 ; free physical = 131 ; free virtual = 3028
INFO: [Timing 38-2] Deriving generated clocks [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.srcs/sources_1/bd/system/ip/system_axi_ethernet_0/bd_0/ip/ip_2/synth/bd_55cd_pcs_pma_0.xdc:42]
Finished Parsing XDC File [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/.Xil/Vivado-22481-aoyagi-VirtualBox/dcp1/system_top_early.xdc]
Parsing XDC File [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/.Xil/Vivado-22481-aoyagi-VirtualBox/dcp1/system_top.xdc]
Finished Parsing XDC File [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/.Xil/Vivado-22481-aoyagi-VirtualBox/dcp1/system_top.xdc]
Parsing XDC File [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/.Xil/Vivado-22481-aoyagi-VirtualBox/dcp1/system_top_late.xdc]
Finished Parsing XDC File [/home/aoyagi/work/square_8/hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/.Xil/Vivado-22481-aoyagi-VirtualBox/dcp1/system_top_late.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2822.234 ; gain = 0.000 ; free physical = 175 ; free virtual = 2975
Restored from archive | CPU: 0.130000 secs | Memory: 0.013687 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2822.234 ; gain = 0.000 ; free physical = 175 ; free virtual = 2975
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 1148 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 57 instances
  IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT, IBUFDS_IBUFDISABLE_INT, INV, OBUFTDS_DCIEN, OBUFTDS_DCIEN): 8 instances
  IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 64 instances
  LUT6_2 => LUT6_2 (LUT5, LUT6): 108 instances
  OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 649 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
  RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 69 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 160 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2017.4.1 (64-bit) build 2117270
open_checkpoint: Time (s): cpu = 00:01:05 ; elapsed = 00:03:05 . Memory (MB): peak = 2822.234 ; gain = 1662.332 ; free physical = 217 ; free virtual = 3014
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx485t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx485t'
INFO: [Common 17-86] Your Implementation license expires in 3 day(s)
INFO: [Common 17-1223] The version limit for your license is '2018.11' and will expire in 5 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command opt_design

Starting DRC Task
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[0] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[0]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[0]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[10] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[10]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[10]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[11] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[11]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[11]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[12] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[12]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[12]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[13] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[13]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[13]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[14] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[14]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[14]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[15] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[15]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[15]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[1] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[1]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[1]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[2] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[2]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[2]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[3] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[3]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[3]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[4] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[4]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[4]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[5] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[5]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[5]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[6] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[6]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[6]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[7] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[7]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[7]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[8] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[8]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[8]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0[9] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[9]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_0/dac_dds_phase_0_0_reg[9]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[0] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[0]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[0]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[10] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[10]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[10]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[11] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[11]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[11]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[12] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[12]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[12]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[13] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[13]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[13]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[14] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[14]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[14]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[15] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[15]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[15]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[1] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[1]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[1]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[2] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[2]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[2]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[3] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[3]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[3]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[4] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[4]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[4]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[5] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[5]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[5]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[6] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[6]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[6]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[7] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[7]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[7]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[8] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[8]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[8]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0[9] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[9]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_1/dac_dds_phase_0_0_reg[9]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[0] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[0]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[0]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[10] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[10]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[10]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[11] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[11]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[11]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[12] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[12]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[12]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[13] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[13]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[13]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[14] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[14]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[14]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[15] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[15]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[15]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[1] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[1]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[1]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[2] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[2]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[2]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[3] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[3]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[3]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[4] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[4]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[4]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[5] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[5]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[5]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[6] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[6]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[6]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[7] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[7]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[7]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[8] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[8]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[8]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0[9] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[9]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_2/dac_dds_phase_0_0_reg[9]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[0] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[0]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[0]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[10] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[10]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[10]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[11] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[11]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[11]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[12] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[12]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[12]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[13] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[13]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[13]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[14] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[14]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[14]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[15] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[15]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[15]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[1] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[1]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[1]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[2] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[2]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[2]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[3] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[3]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[3]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[4] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[4]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[4]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[5] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[5]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[5]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[6] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[6]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[6]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[7] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[7]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[7]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[8] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[8]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[8]__0/Q.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0[9] has multiple drivers: i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[9]/Q, and i_system_wrapper/system_i/axi_ad9144_core/inst/i_core/i_channel_3/dac_dds_phase_0_0_reg[9]__0/Q.
INFO: [Project 1-461] DRC finished with 64 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:01 . Memory (MB): peak = 2830.238 ; gain = 8.000 ; free physical = 205 ; free virtual = 3011
INFO: [Common 17-83] Releasing license: Implementation
15 Infos, 0 Warnings, 0 Critical Warnings and 65 Errors encountered.
opt_design failed
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Sun Nov 25 01:22:07 2018...
[Sun Nov 25 01:22:10 2018] impl_1 finished
wait_on_run: Time (s): cpu = 00:01:18 ; elapsed = 00:03:41 . Memory (MB): peak = 3424.977 ; gain = 0.000 ; free physical = 1799 ; free virtual = 4636
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Sun Nov 25 01:22:14 2018...

What is wrong?

Yuta

Hi Yuta,

The axi_ad9144_core runs at 250 MHz for maximum sampling rate (1GHz), this means to keep up with the DAC you must have 4 parallel data paths.

I see some strange errors in your code.
This is a diff to something I've written, that has built successfully.

diff --git a/library/axi_ad9144/axi_ad9144_channel.v b/library/axi_ad9144/axi_ad9144_channel.v
index 75635a40..5a93392c 100644
--- a/library/axi_ad9144/axi_ad9144_channel.v
+++ b/library/axi_ad9144/axi_ad9144_channel.v
@@ -82,6 +82,10 @@ module axi_ad9144_channel #(
   reg     [15:0]  dac_dds_incr_0 = 'd0;
   reg     [15:0]  dac_dds_incr_1 = 'd0;
   reg     [63:0]  dac_dds_data = 'd0;
+  reg     [15:0]  square_wave_0 = 'd0;
+  reg     [15:0]  square_wave_1 = 'd0;
+  reg     [15:0]  square_wave_2 = 'd0;
+  reg     [15:0]  square_wave_3 = 'd0;
 
   // internal signals
 
@@ -176,7 +180,7 @@ module axi_ad9144_channel #(
       pn7 = dout;
     end
   endfunction
-  
+
   // PN15 function
 
   function [63:0] pn15;
@@ -266,7 +270,7 @@ module axi_ad9144_channel #(
       4'h6: dac_data <= dac_pn7_data_s;
       4'h5: dac_data <= dac_pn15_data_i_s;
       4'h4: dac_data <= dac_pn7_data_i_s;
-      4'h3: dac_data <= 64'd0;
+      4'h3: dac_data <= {square_wave_3,square_wave_2,square_wave_1,square_wave_0};
       4'h2: dac_data <= dma_data;
       4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
                           dac_pat_data_2_s, dac_pat_data_1_s};
@@ -286,6 +290,13 @@ module axi_ad9144_channel #(
     end
   end
 
+  always @(posedge dac_clk) begin
+    square_wave_0 <= {16{dac_dds_phase_0_0[15]}};
+    square_wave_1 <= {16{dac_dds_phase_1_0[15]}};
+    square_wave_2 <= {16{dac_dds_phase_2_0[15]}};
+    square_wave_3 <= {16{dac_dds_phase_3_0[15]}};
+  end
+
   // dds
 
   always @(posedge dac_clk) begin
@@ -331,7 +342,7 @@ module axi_ad9144_channel #(
     .dds_data (dac_dds_data_0_s));
   end
   endgenerate
-  
+
   generate
   if (DATAPATH_DISABLE == 1) begin
   assign dac_dds_data_1_s = 16'd0;
@@ -346,7 +357,7 @@ module axi_ad9144_channel #(

Can you compare what you have whit this, and let me know if have questions about it.

Andrei

Hi, Andrei

I made corrections with reference to your program.
As a result of building, I succeeded in building.

I ran it with SDK in the same way as before.

Then the following waveform was output.
It was a waveform that was not  the square wave.

What should I do?

Yuta

Hi,

Have you simulated the code?
At what frequency have you set the DDS, try more frequency ranges....
What changes have you done to the analog side of the daq2?

Andrei