Square wave output using fmcdaq2

Dear EngineerZone community


Please support.

I am currently creating a communication system.
The concept is to generate an information signal with vc707 and output it as a Square wave from the DAC (ad 9144) of fmcdaq2. Then, the output Square wave is input to the modulator and communication is carried out.

Before that, I am trying to output a Square wave of 1 kHz (offset 0V) from DAC (AD9144) of fmcdaq2.
How can I do it?

Can you create a design as per the user guide and store a Square wave in the buffer?

I can use both Linux / no-OS.

Yuta

Parents Reply
  • HI, Thank you for reply.

    I noticed that I made a mistake.The UART message was displayed properly. I'm sorry.

    In order to select the right path on the mux, I changed "DAC_SRC_ZERO" of L123 to "DAC_SRC_SQUARE"  in /no-OS/common_drivers/dac_core/dac_core.h. And I changed L640 to L654 in /no-OS/fmcdaq2/fmcdaq2.c as follows.

    #if DMA_BUFFER
    	ad9144_channels[0].sel = DAC_SRC_SQUARE;
    	ad9144_channels[1].sel = DAC_SRC_SQUARE;
    	dac_data_setup(&ad9144_core);
    
    	/*if(!dmac_start_transaction(ad9144_dma)) {
    		printf("daq2: transmit data from memory\n");
    	};*/
    #else
    	ad9144_channels[0].sel = DAC_SRC_DDS;
    	ad9144_channels[1].sel = DAC_SRC_DDS;
    	dac_data_setup(&ad9144_core);
    
    	printf("daq2: setup and configuration is done\n");
    #endif

    Others have not changed both hdl and no-OS. (Except axi_ad 9144_channel.v)

    Debugging was done, but 0 was output on the oscilloscope. What should I do?

    I used xsdb. 

    How can I connect to the PS7 and directly read and write registers?

Children
  • 0
    •  Analog Employees 
    on Nov 19, 2018 7:28 AM in reply to matsu.yu.11

    Hi,

    adc and dac core setup at 500MHz that is bad.
    You have pn mismatch, This means your communication between FPGA and devices is not working.
    Let's start with this. What sampling rates do you intend to use, lane rates?

    Andrei

  • Hi, Thank you for your reply.

    I understood that.

    The sampling rate of the lane rate is as follows.

    In the above example, I am using case 3.

    switch (mode) {
    		case '4':
    			printf ("4 - ADC  600 MSPS; DAC  600 MSPS\n");
    			p_ad9523_param->pll2_vco_diff_m1 = 5;
    			(&p_ad9523_param->channels[DAC_FPGA_CLK])->
    					channel_divider = 2;
    			(&p_ad9523_param->channels[DAC_DEVICE_CLK])->
    					channel_divider = 1;
    			(&p_ad9523_param->channels[DAC_DEVICE_SYSREF])->
    					channel_divider = 128;
    			(&p_ad9523_param->channels[DAC_FPGA_SYSREF])->
    					channel_divider = 128;
    			(&p_ad9523_param->channels[ADC_FPGA_CLK])->
    					channel_divider = 2;
    			(&p_ad9523_param->channels[ADC_DEVICE_CLK])->
    					channel_divider = 1;
    			(&p_ad9523_param->channels[ADC_DEVICE_SYSREF])->
    					channel_divider = 128;
    			(&p_ad9523_param->channels[ADC_FPGA_SYSREF])->
    					channel_divider = 128;
    			p_ad9144_xcvr->reconfig_bypass = 0;
    			p_ad9144_param->lane_rate_kbps = 6000000;
    			p_ad9144_xcvr->lane_rate_kbps = 6000000;
    			p_ad9144_xcvr->ref_clock_khz = 300000;
    			p_ad9680_xcvr->reconfig_bypass = 0;
    			p_ad9680_param->lane_rate_kbps = 6000000;
    			p_ad9680_xcvr->lane_rate_kbps = 6000000;
    			p_ad9680_xcvr->ref_clock_khz = 300000;
    #ifdef XILINX
    			p_ad9144_xcvr->dev.lpm_enable = 0;
    			p_ad9144_xcvr->dev.qpll_enable = 0;
    			p_ad9144_xcvr->dev.out_clk_sel = 4;
    
    			p_ad9680_xcvr->dev.lpm_enable = 1;
    			p_ad9680_xcvr->dev.qpll_enable = 0;
    			p_ad9680_xcvr->dev.out_clk_sel = 4;
    #endif
    			break;
    		case '3':
    			printf ("3 - ADC  500 MSPS; DAC  500 MSPS\n");
    			p_ad9523_param->pll2_vco_diff_m1 = 3;
    			(&p_ad9523_param->channels[DAC_FPGA_CLK])->
    					channel_divider = 4;
    			(&p_ad9523_param->channels[DAC_DEVICE_CLK])->
    					channel_divider = 2;
    			(&p_ad9523_param->channels[DAC_DEVICE_SYSREF])->
    					channel_divider = 256;
    			(&p_ad9523_param->channels[DAC_FPGA_SYSREF])->
    					channel_divider = 256;
    			(&p_ad9523_param->channels[ADC_FPGA_CLK])->
    					channel_divider = 4;
    			(&p_ad9523_param->channels[ADC_DEVICE_CLK])->
    					channel_divider = 2;
    			(&p_ad9523_param->channels[ADC_DEVICE_SYSREF])->
    					channel_divider = 256;
    			(&p_ad9523_param->channels[ADC_FPGA_SYSREF])->
    					channel_divider = 256;
    			p_ad9144_xcvr->reconfig_bypass = 0;
    			p_ad9144_param->lane_rate_kbps = 5000000;
    			p_ad9144_xcvr->lane_rate_kbps = 5000000;
    			p_ad9144_xcvr->ref_clock_khz = 250000;
    			p_ad9680_xcvr->reconfig_bypass = 0;
    			p_ad9680_param->lane_rate_kbps = 5000000;
    			p_ad9680_xcvr->lane_rate_kbps = 5000000;
    			p_ad9680_xcvr->ref_clock_khz = 250000;
    #ifdef XILINX
    			p_ad9144_xcvr->dev.lpm_enable = 1;
    			p_ad9144_xcvr->dev.qpll_enable = 0;
    			p_ad9144_xcvr->dev.out_clk_sel = 4;
    
    			p_ad9680_xcvr->dev.lpm_enable = 1;
    			p_ad9680_xcvr->dev.qpll_enable = 0;
    			p_ad9680_xcvr->dev.out_clk_sel = 4;
    #endif
    			break;
    		case '2':
    			printf ("2 - ADC  500 MSPS; DAC 1000 MSPS\n");
    			p_ad9523_param->pll2_vco_diff_m1 = 3;
    			(&p_ad9523_param->channels[DAC_FPGA_CLK])->
    					channel_divider = 2;
    			(&p_ad9523_param->channels[DAC_DEVICE_CLK])->
    					channel_divider = 1;
    			(&p_ad9523_param->channels[DAC_DEVICE_SYSREF])->
    					channel_divider = 128;
    			(&p_ad9523_param->channels[DAC_FPGA_SYSREF])->
    					channel_divider = 128;
    			(&p_ad9523_param->channels[ADC_FPGA_CLK])->
    					channel_divider = 4;
    			(&p_ad9523_param->channels[ADC_DEVICE_CLK])->
    					channel_divider = 2;
    			(&p_ad9523_param->channels[ADC_DEVICE_SYSREF])->
    					channel_divider = 256;
    			(&p_ad9523_param->channels[ADC_FPGA_SYSREF])->
    					channel_divider = 256;
    			p_ad9144_xcvr->reconfig_bypass = 0;
    			p_ad9144_param->lane_rate_kbps = 10000000;
    			p_ad9144_xcvr->lane_rate_kbps = 10000000;
    			p_ad9144_xcvr->ref_clock_khz = 500000;
    			p_ad9680_xcvr->reconfig_bypass = 0;
    			p_ad9680_param->lane_rate_kbps = 5000000;
    			p_ad9680_xcvr->lane_rate_kbps = 5000000;
    			p_ad9680_xcvr->ref_clock_khz = 250000;
    #ifdef XILINX
    			p_ad9144_xcvr->dev.lpm_enable = 0;
    			p_ad9144_xcvr->dev.qpll_enable = 1;
    			p_ad9144_xcvr->dev.out_clk_sel = 4;
    
    			p_ad9680_xcvr->dev.lpm_enable = 1;
    			p_ad9680_xcvr->dev.qpll_enable = 0;
    			p_ad9680_xcvr->dev.out_clk_sel = 4;
    #endif
    			break;
    		default:
    			printf ("1 - ADC 1000 MSPS; DAC 1000 MSPS\n");
    			p_ad9144_xcvr->ref_clock_khz = 500000;
    			p_ad9680_xcvr->ref_clock_khz = 500000;
    			break;
    	}
    

    Yuta

  • 0
    •  Analog Employees 
    on Nov 19, 2018 2:59 PM in reply to matsu.yu.11

    Hi,

    The messages with SYSREF alignment  ERROR made me presume your link is down.
    The setup is ok, sorry for the miss understanding. I forgot that the software takes into consideration the clock ratio. https://github.com/analogdevicesinc/no-OS/blob/master/common_drivers/adc_core/adc_core.c#L114

    https://github.com/analogdevicesinc/hdl/blob/master/projects/daq2/common/daq2_bd.tcl#L143
    https://wiki.analog.com/resources/fpga/docs/axi_ad9144


    An example of how to use xsdb console

     

    $ xsdb
    
    ****** Xilinx System Debugger (XSDB) v2017.4.1
      **** Build date : Jan 30 2018-15:42:35
        ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
    
    
    xsdb% connect
    tcfchan#0
    xsdb% target
      1  APU
         2  ARM Cortex-A9 MPCore #0 (Running)
         3  ARM Cortex-A9 MPCore #1 (Running)
      4  xc7z045
    xsdb% target 2
    xsdb% stop
    Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x113d0c (Suspended)
    xsdb% mrd -force 0x44A00000 
    44A00000:   DEADDEAD
    
    xsdb% mrd -force 0x44A00000
    44A00000:   DEADDEAD
    
    xsdb% mrd -force 0x44A10000 
    44A10000:   000A0062
    
    xsdb% mrd -force 0x44A04418
    44A04418:   00000000
    
    xsdb% mwr -force 0x44A04418 0x3
    xsdb% mrd -force 0x44A04418
    44A04418:   00000003
    
    xsdb% exit
    


    First, can you confirm the DDS generator works on your system?

    Andrei

  • Hi,

    After programming to the FPGA, I tried using xdbd.
    The results are shown below.

    xsdb% connect                                                                   
    tcfchan#0                                                                       
    xsdb% target                                                                    
      1  xc7vx485t
         2  MicroBlaze Debug Module at USER2
            3  MicroBlaze #0 (Stop)
    xsdb% target 3                                                                  
    xsdb% mrd -force 0x44A00000                                                     
    44A00000:   DEADDEAD
    
    xsdb% mrd -force 0x44A10000                                                     
    44A10000:   000A0062
    
    xsdb% mrd -force 0x44A04418                                                     
    44A04418:   00000000
    
    xsdb% mwr -force 0x44A04418 0x3                                                 
    xsdb% mrd -force 0x44A04418                                                     
    44A04418:   00000003
    
    xsdb% exit                                                                      
    exit

    After that I ran with SDK, but as before, PN mismatch occurred.

    Available sampling rates:
    	1 - ADC 1000 MSPS; DAC 1000 MSPS
    	2 - ADC  500 MSPS; DAC 1000 MSPS
    	3 - ADC  500 MSPS; DAC  500 MSPS
    	4 - ADC  600 MSPS; DAC  600 MSPS
    choose an option [default 1]:
    3 - ADC  500 MSPS; DAC  500 MSPS
    
    CPLL ENABLE
    
    CPLL ENABLE
    Tx link is enabled
    Measured Link Clock: 125 MHz
    Link status: DATA
    SYSREF captured: Yes
    SYSREF alignment ERROR
    Rx link is enabled
    Measured Link Clock: 125 MHz
    Link status: DATA
    SYSREF captured: Yes
    SYSREF alignment ERROR
    adc_setup adc core initialized (500 MHz).
    dac_setup dac core initialized (500 MHz).
    main ad9680 - PN9 sequence mismatch!
    main ad9680 - PN23 sequence mismatch!
    daq2: RX capture done.

    No waveform was output at all.

    After that, if you rewrite 0x44A04418 to 0x0 with xsbd, the sine waveform was output.

    Yuta

  • 0
    •  Analog Employees 
    on Nov 20, 2018 8:50 AM in reply to matsu.yu.11

    Hi,

    Any changes to hardware or clock/rates that you haven't mentioned?
    I've seen in other threads problems caused by ILA's with no timing issue reported. Do you have ILA's in the system?
    Better of can you start fresh on a new workspace hdl_2018_r1 and no-Os 2018_r1? Validate that the design is working, then add only the last discussed square wave generator in HDL.

    Andrei