Square wave output using fmcdaq2

Dear EngineerZone community


Please support.

I am currently creating a communication system.
The concept is to generate an information signal with vc707 and output it as a Square wave from the DAC (ad 9144) of fmcdaq2. Then, the output Square wave is input to the modulator and communication is carried out.

Before that, I am trying to output a Square wave of 1 kHz (offset 0V) from DAC (AD9144) of fmcdaq2.
How can I do it?

Can you create a design as per the user guide and store a Square wave in the buffer?

I can use both Linux / no-OS.

Yuta

Parents
  • 0
    •  Analog Employees 
    on Oct 10, 2018 8:08 AM

    Hi,

    I'm confused, ad9144 is a high speed dac (1GSPS), why do you want it to output a squarewave of 1KHz?
    The daq2 board has some filters on the output, you will have to change those to be able to transmit a sqare wave.

    Take a look at https://ez.analog.com/fpga/f/q-a/81027/daq2-kcu105-send-data-to-dac


    Are you familiar with our RF designs? If not, it may be of interest to you.

    www.analog.com/en/products/adrv9008-2.html

    www.analog.com/.../ad9361.html
    wiki.analog.com/.../adrv936x_rfsom

    Andrei

  • Thank you,Andrei

    I am sorry for confusing you.I wanted to generate a square wave of 1 kHz because the modulator used operates by inputting a square wave of about 1 kHz to 2 kHz.

    However, since the ADC/DAC I have is fmcdaq2, I would like to know haw to output a 1 kHz Square wave using fmcdaq2.

    I'm sorry. I looked at https://ez.analog.com/fpga/f/q-a/81027/daq2-kcu105-send-data-to-dac and I saw the URL and could understand changing the filter of fmcdaq2, but I could not understand which part to change specifically.

    Please tell me.

    Yuta

  • Hi,

    I use hdl_2018_r1 for hdl and 2018_R1 for no-OS.

    I could output rectangular wave.

    However, I would like to output a rectangular wave between 1 kHz and 10 kHz.
    How can I implement it by changing fmcdaq2.c?

  • 0
    •  Analog Employees 
    on Nov 8, 2018 12:51 PM in reply to matsu.yu.11

    Hi,


    Again, why don't you simply use a GPIO not the daq2 for that?
    A few ideas:

    1. You can use the software to toggle a register or send/change a value at your desired frequency.
    2. Use the software to write values directly in an HDL register(that you add), in the register map, as an example see dac_data_select_s (0x4418 REG_CHAN_CNTRL_7),

    Feed it to the data select multiplexer https://github.com/analogdevicesinc/hdl/blob/hdl_2018_r1/library/axi_ad9144/axi_ad9144_channel.v#L269

    3. Write in HDL something like:

    input [31: 0] increment //from the regmap

    reg [15:0] square_wave = 0;


    always @(pesedge clk) begin
       sawtooth_wave <= sawtooth_wave + increment;

       square_wave <= {16{sawtooth_wave[31]}}
    end

    The frequency of your square wave is core _clock/(2^32 * increment)
    use the above to calculate the value for increment.

    https://en.wikipedia.org/wiki/Numerically_controlled_oscillator

    You get the idea, output that trough the multiplexer mentioned above.

    Andrei

  • Hi, Thank you for your reply.

    I could understand what you said.

    However, I wanted to see the example ( dac_data_select_s (0x4418 REG_CHAN_CNTRL_7),) and I looked for it, but I could not find it.

    Where is it?

    Also, as described in the attached file, is it correct by adding the description of HDL (Number 3 of a few ideas) to axi_ad 9144_channnel.v and changing the multiplexer description to dac_data_sel_s == 4'h3 and 4'h3: dac_data <= square_wave; ? (from L266 toL290)

    // ***************************************************************************
    // ***************************************************************************
    // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
    //
    // In this HDL repository, there are many different and unique modules, consisting
    // of various HDL (Verilog or VHDL) components. The individual modules are
    // developed independently, and may be accompanied by separate and unique license
    // terms.
    //
    // The user should read each of these license terms, and understand the
    // freedoms and responsibilities that he or she has by using this source/core.
    //
    // This core is distributed in the hope that it will be useful, but WITHOUT ANY
    // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
    // A PARTICULAR PURPOSE.
    //
    // Redistribution and use of source or resulting binaries, with or without modification
    // of this file, are permitted under one of the following two license terms:
    //
    //   1. The GNU General Public License version 2 as published by the
    //      Free Software Foundation, which can be found in the top level directory
    //      of this repository (LICENSE_GPL2), and also online at:
    //      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
    //
    // OR
    //
    //   2. An ADI specific BSD license, which can be found in the top level directory
    //      of this repository (LICENSE_ADIBSD), and also on-line at:
    //      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
    //      This will allow to generate bit files and not release the source code,
    //      as long as it attaches to an ADI device.
    //
    // ***************************************************************************
    // ***************************************************************************
    
    `timescale 1ns/100ps
    
    module axi_ad9144_channel #(
    
      parameter CHANNEL_ID = 32'h0,
      parameter DATAPATH_DISABLE = 0) (
    
      // dac interface
    
      input                   dac_clk,
      input                   dac_rst,
      output  reg             dac_enable,
      output  reg [63:0]      dac_data,
      input       [63:0]      dma_data,
    
      // processor interface
    
      input                   dac_data_sync,
      input                   dac_dds_format,
    
      // bus interface
    
      input                   up_rstn,
      input                   up_clk,
      input                   up_wreq,
      input       [13:0]      up_waddr,
      input       [31:0]      up_wdata,
      output                  up_wack,
      input                   up_rreq,
      input       [13:0]      up_raddr,
      output      [31:0]      up_rdata,
      output                  up_rack);
    
      
    
      // internal registers
    
      reg     [63:0]  dac_pn7_data = 'd0;
      reg     [63:0]  dac_pn15_data = 'd0;
      reg     [15:0]  dac_dds_phase_0_0 = 'd0;
      reg     [15:0]  dac_dds_phase_0_1 = 'd0;
      reg     [15:0]  dac_dds_phase_1_0 = 'd0;
      reg     [15:0]  dac_dds_phase_1_1 = 'd0;
      reg     [15:0]  dac_dds_phase_2_0 = 'd0;
      reg     [15:0]  dac_dds_phase_2_1 = 'd0;
      reg     [15:0]  dac_dds_phase_3_0 = 'd0;
      reg     [15:0]  dac_dds_phase_3_1 = 'd0;
      reg     [15:0]  dac_dds_incr_0 = 'd0;
      reg     [15:0]  dac_dds_incr_1 = 'd0;
      reg     [63:0]  dac_dds_data = 'd0;
    
     
    
      // internal signals
    
      wire    [15:0]  dac_dds_data_0_s;
      wire    [15:0]  dac_dds_data_1_s;
      wire    [15:0]  dac_dds_data_2_s;
      wire    [15:0]  dac_dds_data_3_s;
      wire    [15:0]  dac_dds_scale_1_s;
      wire    [15:0]  dac_dds_init_1_s;
      wire    [15:0]  dac_dds_incr_1_s;
      wire    [15:0]  dac_dds_scale_2_s;
      wire    [15:0]  dac_dds_init_2_s;
      wire    [15:0]  dac_dds_incr_2_s;
      wire    [15:0]  dac_pat_data_1_s;
      wire    [15:0]  dac_pat_data_2_s;
      wire    [ 3:0]  dac_data_sel_s;
      wire    [63:0]  dac_pn7_data_i_s;
      wire    [63:0]  dac_pn15_data_i_s;
      wire    [63:0]  dac_pn7_data_s;
      wire    [63:0]  dac_pn15_data_s;
    
       // PN7 function
    
      function [63:0] pn7;
        input [7:0] din;
        reg   [63:0] dout;
        begin
          dout[15] = din[ 6] ^ din[ 5];
          dout[14] = din[ 5] ^ din[ 4];
          dout[13] = din[ 4] ^ din[ 3];
          dout[12] = din[ 3] ^ din[ 2];
          dout[11] = din[ 2] ^ din[ 1];
          dout[10] = din[ 1] ^ din[ 0];
          dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5];
          dout[ 8] = din[ 6] ^ din[ 4];
          dout[ 7] = din[ 5] ^ din[ 3];
          dout[ 6] = din[ 4] ^ din[ 2];
          dout[ 5] = din[ 3] ^ din[ 1];
          dout[ 4] = din[ 2] ^ din[ 0];
          dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5];
          dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4];
          dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
          dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
          dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
          dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
          dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5];
          dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4];
          dout[27] = din[ 0] ^ din[ 6] ^ din[ 3];
          dout[26] = din[ 6] ^ din[ 2];
          dout[25] = din[ 5] ^ din[ 1];
          dout[24] = din[ 4] ^ din[ 0];
          dout[23] = din[ 3] ^ din[ 6] ^ din[ 5];
          dout[22] = din[ 2] ^ din[ 5] ^ din[ 4];
          dout[21] = din[ 1] ^ din[ 4] ^ din[ 3];
          dout[20] = din[ 0] ^ din[ 3] ^ din[ 2];
          dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
          dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
          dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
          dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4];
          dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3];
          dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2];
          dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1];
          dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
          dout[43] = din[ 1] ^ din[ 3] ^ din[ 6];
          dout[42] = din[ 0] ^ din[ 5] ^ din[ 2];
          dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1];
          dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0];
          dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5];
          dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4];
          dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3];
          dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2];
          dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1];
          dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0];
          dout[33] = din[ 0] ^ din[ 2] ^ din[ 6];
          dout[32] = din[ 6] ^ din[ 1];
          dout[63] = din[ 5] ^ din[ 0];
          dout[62] = din[ 4] ^ din[ 6] ^ din[ 5];
          dout[61] = din[ 3] ^ din[ 5] ^ din[ 4];
          dout[60] = din[ 2] ^ din[ 4] ^ din[ 3];
          dout[59] = din[ 1] ^ din[ 3] ^ din[ 2];
          dout[58] = din[ 0] ^ din[ 2] ^ din[ 1];
          dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0];
          dout[56] = din[ 0] ^ din[ 4] ^ din[ 6];
          dout[55] = din[ 6] ^ din[ 3];
          dout[54] = din[ 5] ^ din[ 2];
          dout[53] = din[ 4] ^ din[ 1];
          dout[52] = din[ 3] ^ din[ 0];
          dout[51] = din[ 2] ^ din[ 6] ^ din[ 5];
          dout[50] = din[ 1] ^ din[ 5] ^ din[ 4];
          dout[49] = din[ 0] ^ din[ 4] ^ din[ 3];
          dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2];
          pn7 = dout;
        end
      endfunction
      
      // PN15 function
    
      function [63:0] pn15;
        input [15:0] din;
        reg   [63:0] dout;
        begin
          dout[15] = din[14] ^ din[13];
          dout[14] = din[13] ^ din[12];
          dout[13] = din[12] ^ din[11];
          dout[12] = din[11] ^ din[10];
          dout[11] = din[10] ^ din[ 9];
          dout[10] = din[ 9] ^ din[ 8];
          dout[ 9] = din[ 8] ^ din[ 7];
          dout[ 8] = din[ 7] ^ din[ 6];
          dout[ 7] = din[ 6] ^ din[ 5];
          dout[ 6] = din[ 5] ^ din[ 4];
          dout[ 5] = din[ 4] ^ din[ 3];
          dout[ 4] = din[ 3] ^ din[ 2];
          dout[ 3] = din[ 2] ^ din[ 1];
          dout[ 2] = din[ 1] ^ din[ 0];
          dout[ 1] = din[ 0] ^ din[14] ^ din[13];
          dout[ 0] = din[14] ^ din[12];
          dout[31] = din[13] ^ din[11];
          dout[30] = din[12] ^ din[10];
          dout[29] = din[11] ^ din[ 9];
          dout[28] = din[10] ^ din[ 8];
          dout[27] = din[ 9] ^ din[ 7];
          dout[26] = din[ 8] ^ din[ 6];
          dout[25] = din[ 7] ^ din[ 5];
          dout[24] = din[ 6] ^ din[ 4];
          dout[23] = din[ 5] ^ din[ 3];
          dout[22] = din[ 4] ^ din[ 2];
          dout[21] = din[ 3] ^ din[ 1];
          dout[20] = din[ 2] ^ din[ 0];
          dout[19] = din[ 1] ^ din[14] ^ din[13];
          dout[18] = din[ 0] ^ din[13] ^ din[12];
          dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11];
          dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10];
          dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
          dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
          dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
          dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
          dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
          dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
          dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
          dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
          dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
          dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
          dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13];
          dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12];
          dout[35] = din[ 0] ^ din[14] ^ din[11];
          dout[34] = din[14] ^ din[10];
          dout[33] = din[13] ^ din[ 9];
          dout[32] = din[12] ^ din[ 8];
          dout[63] = din[11] ^ din[ 7];
          dout[62] = din[10] ^ din[ 6];
          dout[61] = din[ 9] ^ din[ 5];
          dout[60] = din[ 8] ^ din[ 4];
          dout[59] = din[ 7] ^ din[ 3];
          dout[58] = din[ 6] ^ din[ 2];
          dout[57] = din[ 5] ^ din[ 1];
          dout[56] = din[ 4] ^ din[ 0];
          dout[55] = din[ 3] ^ din[14] ^ din[13];
          dout[54] = din[ 2] ^ din[13] ^ din[12];
          dout[53] = din[ 1] ^ din[12] ^ din[11];
          dout[52] = din[ 0] ^ din[11] ^ din[10];
          dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9];
          dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8];
          dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7];
          dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6];
          pn15 = dout;
        end
      endfunction
    
      assign dac_pn7_data_i_s  = ~dac_pn7_data;
      assign dac_pn15_data_i_s = ~dac_pn15_data;
    
      assign dac_pn7_data_s    = dac_pn7_data;
      assign dac_pn15_data_s   = dac_pn15_data;
    
    
    
    
      //my scripts
      
      input       [31:0]      increment,
      reg [15:0] square_wave = 0;
      
      always @(pesedge clk)begin
        sawtooth_wave <= sawtooth_wave + increment;
        square_wave <= {16{sawtooth_wave[31]}}
      end
      // dac data select
    
      always @(posedge dac_clk) begin
        dac_enable <= (dac_data_sel_s == 4'h3) ? 1'b1 : 1'b0;
        case (dac_data_sel_s)
          4'h7: dac_data <= dac_pn15_data_s;
          4'h6: dac_data <= dac_pn7_data_s;
          4'h5: dac_data <= dac_pn15_data_i_s;
          4'h4: dac_data <= dac_pn7_data_i_s;
          4'h3: dac_data <= square_wave;
          4'h2: dac_data <= dma_data;
          4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
                              dac_pat_data_2_s, dac_pat_data_1_s};
          default: dac_data <= dac_dds_data;
        endcase
      end
      
      
    
      // pn registers
    
      always @(posedge dac_clk) begin
        if (dac_data_sync == 1'b1) begin
          dac_pn7_data <= {64{1'd1}};
          dac_pn15_data <= {64{1'd1}};
        end else begin
          dac_pn7_data <= pn7(dac_pn7_data[55:48]);
          dac_pn15_data <= pn15(dac_pn15_data[63:48]);
        end
      end
    
      // dds
    
      always @(posedge dac_clk) begin
        if (dac_data_sync == 1'b1) begin
          dac_dds_phase_0_0 <= dac_dds_init_1_s;
          dac_dds_phase_0_1 <= dac_dds_init_2_s;
          dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
          dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
          dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
          dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
          dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
          dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
          dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0};
          dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0};
          dac_dds_data <= 64'd0;
        end else begin
          dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
          dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
          dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
          dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
          dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
          dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
          dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
          dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
          dac_dds_incr_0 <= dac_dds_incr_0;
          dac_dds_incr_1 <= dac_dds_incr_1;
          dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s,
                            dac_dds_data_1_s, dac_dds_data_0_s};
        end
      end
    
      generate
      if (DATAPATH_DISABLE == 1) begin
      assign dac_dds_data_0_s = 16'd0;
      end else begin
      ad_dds i_dds_0 (
        .clk (dac_clk),
        .dds_format (dac_dds_format),
        .dds_phase_0 (dac_dds_phase_0_0),
        .dds_scale_0 (dac_dds_scale_1_s),
        .dds_phase_1 (dac_dds_phase_0_1),
        .dds_scale_1 (dac_dds_scale_2_s),
        .dds_data (dac_dds_data_0_s));
      end
      endgenerate
      
      generate
      if (DATAPATH_DISABLE == 1) begin
      assign dac_dds_data_1_s = 16'd0;
      end else begin
      ad_dds i_dds_1 (
        .clk (dac_clk),
        .dds_format (dac_dds_format),
        .dds_phase_0 (dac_dds_phase_1_0),
        .dds_scale_0 (dac_dds_scale_1_s),
        .dds_phase_1 (dac_dds_phase_1_1),
        .dds_scale_1 (dac_dds_scale_2_s),
        .dds_data (dac_dds_data_1_s));
      end
      endgenerate
      
      generate
      if (DATAPATH_DISABLE == 1) begin
      assign dac_dds_data_2_s = 16'd0;
      end else begin
      ad_dds i_dds_2 (
        .clk (dac_clk),
        .dds_format (dac_dds_format),
        .dds_phase_0 (dac_dds_phase_2_0),
        .dds_scale_0 (dac_dds_scale_1_s),
        .dds_phase_1 (dac_dds_phase_2_1),
        .dds_scale_1 (dac_dds_scale_2_s),
        .dds_data (dac_dds_data_2_s));
      end
      endgenerate
      
      generate
      if (DATAPATH_DISABLE == 1) begin
      assign dac_dds_data_3_s = 16'd0;
      end else begin
      ad_dds i_dds_3 (
        .clk (dac_clk),
        .dds_format (dac_dds_format),
        .dds_phase_0 (dac_dds_phase_3_0),
        .dds_scale_0 (dac_dds_scale_1_s),
        .dds_phase_1 (dac_dds_phase_3_1),
        .dds_scale_1 (dac_dds_scale_2_s),
        .dds_data (dac_dds_data_3_s));
      end
      endgenerate
      
      // single channel processor
    
      up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
        .dac_clk (dac_clk),
        .dac_rst (dac_rst),
        .dac_dds_scale_1 (dac_dds_scale_1_s),
        .dac_dds_init_1 (dac_dds_init_1_s),
        .dac_dds_incr_1 (dac_dds_incr_1_s),
        .dac_dds_scale_2 (dac_dds_scale_2_s),
        .dac_dds_init_2 (dac_dds_init_2_s),
        .dac_dds_incr_2 (dac_dds_incr_2_s),
        .dac_pat_data_1 (dac_pat_data_1_s),
        .dac_pat_data_2 (dac_pat_data_2_s),
        .dac_data_sel (dac_data_sel_s),
        .dac_iq_mode (),
        .dac_iqcor_enb (),
        .dac_iqcor_coeff_1 (),
        .dac_iqcor_coeff_2 (),
        .up_usr_datatype_be (),
        .up_usr_datatype_signed (),
        .up_usr_datatype_shift (),
        .up_usr_datatype_total_bits (),
        .up_usr_datatype_bits (),
        .up_usr_interpolation_m (),
        .up_usr_interpolation_n (),
        .dac_usr_datatype_be (1'b0),
        .dac_usr_datatype_signed (1'b1),
        .dac_usr_datatype_shift (8'd0),
        .dac_usr_datatype_total_bits (8'd16),
        .dac_usr_datatype_bits (8'd16),
        .dac_usr_interpolation_m (16'd1),
        .dac_usr_interpolation_n (16'd1),
        .up_rstn (up_rstn),
        .up_clk (up_clk),
        .up_wreq (up_wreq),
        .up_waddr (up_waddr),
        .up_wdata (up_wdata),
        .up_wack (up_wack),
        .up_rreq (up_rreq),
        .up_raddr (up_raddr),
        .up_rdata (up_rdata),
        .up_rack (up_rack));
      
    endmodule
    
    // ***************************************************************************
    // ***************************************************************************
    
      
    

    Please teach me.

  • 0
    •  Analog Employees 
    on Nov 14, 2018 8:40 AM in reply to matsu.yu.11

    Hi,

    This is the function you are looking for:https://github.com/analogdevicesinc/no-OS/blob/2018_R1/common_drivers/dac_core/dac_core.c#L176

    The code I gave you is to help you understand the principle, I see that you've taken it as it is.
    To get you faster to implementation: in principle, in the code you posted above "sawtooth_wave" is the same thing with "dac_dds_phase_0_0". Replacing sawtooth_wave with dac_dds_phase_0_0 will give you a square wave frequency equal with the DDS sine frequency. The data select and the value for frequency is all you have to modify in the software.
    Line 271 use dac_clk not clk.

    Andrei

  • Hi, Thank you for reply.

    I understood what you were saying. Thank you.

    I changed "sawtooth_wave" to "dac_dds_phase_0_0"  and changed "clk" to "dac_clk" in axi_9144_channel.v .

    And then I ran make in /library/axi_ad 9144 and then executed make in /projects/daq2/vc707.

    As a result, the build succeeded.

    However, when executed with SDK, no UART message was displayed and a noise waveform was output.

    Is it wrong to write mux?

      always @(posedge dac_clk) begin
        dac_enable <= (dac_data_sel_s == 4'h3) ? 1'b1 : 1'b0;
        case (dac_data_sel_s)
          4'h7: dac_data <= dac_pn15_data_s;
          4'h6: dac_data <= dac_pn7_data_s;
          4'h5: dac_data <= dac_pn15_data_i_s;
          4'h4: dac_data <= dac_pn7_data_i_s;
          4'h3: dac_data <= square_wave;
          4'h2: dac_data <= dma_data;
          4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
                              dac_pat_data_2_s, dac_pat_data_1_s};
          default: dac_data <= dac_dds_data;
        endcase
      end
      

    Or is it because the value is not stored in "implement"? In that case, how can I give a value to "imlpement"?

    please tell me.

Reply
  • Hi, Thank you for reply.

    I understood what you were saying. Thank you.

    I changed "sawtooth_wave" to "dac_dds_phase_0_0"  and changed "clk" to "dac_clk" in axi_9144_channel.v .

    And then I ran make in /library/axi_ad 9144 and then executed make in /projects/daq2/vc707.

    As a result, the build succeeded.

    However, when executed with SDK, no UART message was displayed and a noise waveform was output.

    Is it wrong to write mux?

      always @(posedge dac_clk) begin
        dac_enable <= (dac_data_sel_s == 4'h3) ? 1'b1 : 1'b0;
        case (dac_data_sel_s)
          4'h7: dac_data <= dac_pn15_data_s;
          4'h6: dac_data <= dac_pn7_data_s;
          4'h5: dac_data <= dac_pn15_data_i_s;
          4'h4: dac_data <= dac_pn7_data_i_s;
          4'h3: dac_data <= square_wave;
          4'h2: dac_data <= dma_data;
          4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
                              dac_pat_data_2_s, dac_pat_data_1_s};
          default: dac_data <= dac_dds_data;
        endcase
      end
      

    Or is it because the value is not stored in "implement"? In that case, how can I give a value to "imlpement"?

    please tell me.

Children