Square wave output using fmcdaq2

matsu.yu.11

on Oct 10, 2018

Dear EngineerZone community

Please support.

I am currently creating a communication system.
The concept is to generate an information signal with vc707 and output it as a Square wave from the DAC (ad 9144) of fmcdaq2. Then, the output Square wave is input to the modulator and communication is carried out.

Before that, I am trying to output a Square wave of 1 kHz (offset 0V) from DAC (AD9144) of fmcdaq2.
How can I do it?

Can you create a design as per the user guide and store a Square wave in the buffer?

I can use both Linux / no-OS．

Yuta

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0 andrei_g

on Oct 10, 2018 4:08 AM
Hi,

I'm confused, ad9144 is a high speed dac (1GSPS), why do you want it to output a squarewave of 1KHz?
The daq2 board has some filters on the output, you will have to change those to be able to transmit a sqare wave.

Take a look at https://ez.analog.com/fpga/f/q-a/81027/daq2-kcu105-send-data-to-dac

Are you familiar with our RF designs? If not, it may be of interest to you.

www.analog.com/en/products/adrv9008-2.html

www.analog.com/.../ad9361.html
wiki.analog.com/.../adrv936x_rfsom

Andrei
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0 matsu.yu.11
on Oct 10, 2018 5:35 AM in reply to andrei_g
Thank you，Andrei

I am sorry for confusing you．I wanted to generate a square wave of 1 kHz because the modulator used operates by inputting a square wave of about 1 kHz to 2 kHz.

However, since the ADC/DAC I have is fmcdaq2, I would like to know haw to output a 1 kHz Square wave using fmcdaq2.

I'm sorry. I looked at https://ez.analog.com/fpga/f/q-a/81027/daq2-kcu105-send-data-to-dac and I saw the URL and could understand changing the filter of fmcdaq2, but I could not understand which part to change specifically.

Please tell me．

Yuta
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0 andrei_g

on Oct 10, 2018 7:24 AM in reply to matsu.yu.11
You have 2 options:
Add code in hdl to generate a square wave, you can use, change directly the dds.

Replace the sine_lut from no-Os with your own square wave.
https://github.com/analogdevicesinc/no-OS/blob/master/common_drivers/dac_buffer/dac_buffer.c

Andrei
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0 matsu.yu.11

on Oct 24, 2018 4:14 AM in reply to andrei_g

Thanks for the reply, Andrei.

Sorry for the late reply.

/***************************************************************************//**
 * @file dac_buffer.c
 * @brief Implementation of DAC LUT driver.
 * @author Istvan Csomortani (istvan.csomortani@analog.com)
 ********************************************************************************
 * Copyright 2014-2016(c) Analog Devices, Inc.
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 * - Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in
 * the documentation and/or other materials provided with the
 * distribution.
 * - Neither the name of Analog Devices, Inc. nor the names of its
 * contributors may be used to endorse or promote products derived
 * from this software without specific prior written permission.
 * - The use of this software may or may not infringe the patent rights
 * of one or more patent holders. This license does not release you
 * from the requirement that you obtain separate licenses from these
 * patent holders to use this software.
 * - Use of the software either in source or binary form, must be run
 * on or directly connected to an Analog Devices Inc. component.
 *
 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
#include "dac_buffer.h"

/******************************************************************************/
/******************************* Constant definitions *************************/
/******************************************************************************/

/* Sine Look Up Table */
static const uint16_t sine_lut[1024] = {
	0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF};

/******************************************************************************/
/************************ Functions Definitions *******************************/
/******************************************************************************/

uint32_t dac_buffer_load(dac_core core, uint32_t start_address) {

	uint32_t no_of_samples;
	uint32_t index_i, index_q;
	uint32_t index_mem = 0;

	no_of_samples = sizeof(sine_lut) / sizeof(typeof(sine_lut[0]));

	for (index_i = 0; index_i < no_of_samples; index_i++) {
		 /* Phase shifted by 90 degree */
		index_q = (index_i + 256) % no_of_samples;

		switch (core.no_of_channels) {
			case 1:
				ad_reg_write_16(start_address + index_mem * 2, sine_lut[index_i]);
				index_mem += 1;
				break;
			case 2:
				ad_reg_write_16(start_address + (index_mem + 0) * 2, sine_lut[index_i]);
				ad_reg_write_16(start_address + (index_mem + 1) * 2, sine_lut[index_q]);
				index_mem += 2;
				break;
			case 4:
				ad_reg_write_16(start_address + (index_mem + 0) * 2, sine_lut[index_i]);
				ad_reg_write_16(start_address + (index_mem + 1) * 2, sine_lut[index_q]);
				ad_reg_write_16(start_address + (index_mem + 2) * 2, sine_lut[index_i]);
				ad_reg_write_16(start_address + (index_mem + 3) * 2, sine_lut[index_q]);
				index_mem += 4;
				break;
			default:
				ad_printf("Unsupported mode.\n\r");
				return -1;
		}
	}

	ad_dcache_flush();

	return (core.no_of_channels * no_of_samples);
}

I replaced sine_lut of no-Os with its own square wave as shown in attached dac_buffer.c.

However, as a result of executing with SDK, Sin waveform was output.

The run console display is as follows.

--------------------------------------------------------------------

Available sampling rates:
1 - ADC 1000 MSPS; DAC 1000 MSPS
2 - ADC 500 MSPS; DAC 1000 MSPS
3 - ADC 500 MSPS; DAC 500 MSPS
4 - ADC 600 MSPS; DAC 600 MSPS
choose an option [default 1]:
3
3 - ADC 500 MSPS; DAC 500 MSPS
ad9144_setup : Device descriptor failed!

CPLL ENABLE

CPLL ENABLE
Tx link is enabled
Measured Link Clock: 125 MHz
Link status: DATA
SYSREF captured: Yes
Rx link is enabled
Measured Link Clock: 125 MHz
Link status: DATA
SYSREF captured: Yes
adc_setup adc core initialized (500 MHz).
dac_setup dac core initialized (500 MHz).
daq2: setup and configuration is done
daq2: RX capture done.

--------------------------------------------------------------------

How can I output square wave? Please tell me.

Yuta

0 andrei_g

on Oct 24, 2018 4:31 AM in reply to matsu.yu.11
Hi Yuta,

https://github.com/analogdevicesinc/no-OS/blob/master/fmcdaq2/fmcdaq2.c#L640

#define DMA_BUFFER
or modify that loop.

Andrei
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0 matsu.yu.11
on Oct 24, 2018 6:57 AM in reply to andrei_g
Hi, Andrei

After commenting out #define DMA_BUFFER 0 of L70 in fmcdaq2.c, I changed #if DMA_BUFFER in L640 to #define DMA_BUFFER and commented out from #else in L618 to #endif in L624.

After that, I ran make with no-OS/fmcdaq2/vc 707, and as a result of running with SDK, it was displayed on the console as follows.

How can I solve it? please teach me.

----------------------------------------------------

Available sampling rates:
1 - ADC 1000 MSPS; DAC 1000 MSPS
2 - ADC 500 MSPS; DAC 1000 MSPS
3 - ADC 500 MSPS; DAC 500 MSPS
4 - ADC 600 MSPS; DAC 600 MSPS
choose an option [default 1]:
4
4 - ADC 600 MSPS; DAC 600 MSPS

CPLL ENABLE
xcvr_setup ERROR: XCVR initialization failed!

CPLL ENABLE
xcvr_setup ERROR: XCVR initialization failed!
Tx link is disabled
Measured Link Clock: off
External reset is deasserted
Rx link is disabled
Measured Link Clock: off
External reset is deasserted
adc_setup adc core Status errors.
dac_setup DAC Core Status errors.

----------------------------------------------------
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0 andrei_g

on Oct 24, 2018 7:08 AM in reply to matsu.yu.11
That is a strange result.
Correction, don't uncomment anything out, just change 0 to 1
https://github.com/analogdevicesinc/no-OS/blob/master/fmcdaq2/fmcdaq2.c#L70

Andrei
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0 matsu.yu.11
on Oct 25, 2018 5:26 AM in reply to andrei_g
I just changed 0 to 1 of https://github.com/analogdevicesinc/no-OS/blob/master/fmcdaq2/fmcdaq2.c#L70.

After that, I ran make with no-OS/fmcdaq2/vc 707, and as a result of running with SDK, it was displayed on the console as follows. The same error occurred

How can I solve it? please teach me.

----------------------------------------------------

Available sampling rates:
1 - ADC 1000 MSPS; DAC 1000 MSPS
2 - ADC 500 MSPS; DAC 1000 MSPS
3 - ADC 500 MSPS; DAC 500 MSPS
4 - ADC 600 MSPS; DAC 600 MSPS
choose an option [default 1]:
1
1 - ADC 1000 MSPS; DAC 1000 MSPS
xcvr_setup ERROR: XCVR initialization failed!
xcvr_setup ERROR: XCVR initialization failed!
Tx link is disabled
Measured Link Clock: off
External reset is deasserted
Rx link is disabled
Measured Link Clock: off
External reset is deasserted
adc_setup adc core Status errors.
dac_setup DAC Core Status errors.

----------------------------------------------------

Also, CDT Build Console is as shown below．Are these errors caused?

----------------------------------------------------

18:15:33 **** Incremental Build of configuration Debug for project sw ****
make all
'Building file: ../src/ad9144.c'
'Invoking: MicroBlaze gcc compiler'
mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/ad9144.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/ad9144.d" -MT"src/ad9144.o" -o "src/ad9144.o" "../src/ad9144.c"
In file included from ../src/platform_drivers.h:47:0,
from ../src/ad9144.c:46:
../src/config.h:70:9: error: expected declaration specifiers or '...' before string constant
printf("\nWARNING no vendor defined in config.h (for carrier)\n");
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/config.h:74:9: error: expected declaration specifiers or '...' before string constant
printf("\nWARNING CPU arch defined in config.h\n");
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from ../src/ad9144.c:46:0:
../src/ad9144.c: In function 'ad9144_spi_check_status':
../src/platform_drivers.h:111:23: warning: implicit declaration of function 'usleep' [-Wimplicit-function-declaration]
#define mdelay(msecs) usleep(1000*msecs)
^
../src/ad9144.c:134:4: note: in expansion of macro 'mdelay'
mdelay(1);
^~~~~~
../src/ad9144.c: In function 'ad9144_short_pattern_test':
../src/ad9144.c:528:50: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t {aka long unsigned int}' [-Wformat=]
printf("%s : short-pattern-test mismatch (0x%x, 0x%x 0x%x, 0x%x)!.\n",
^
../src/ad9144.c:528:56: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'uint32_t {aka long unsigned int}' [-Wformat=]
printf("%s : short-pattern-test mismatch (0x%x, 0x%x 0x%x, 0x%x)!.\n",
^
../src/ad9144.c:528:61: warning: format '%x' expects argument of type 'unsigned int', but argument 5 has type 'uint32_t {aka const long unsigned int}' [-Wformat=]
printf("%s : short-pattern-test mismatch (0x%x, 0x%x 0x%x, 0x%x)!.\n",
^
make: *** [src/ad9144.o] error 1

18:15:38 Build Finished (took 4s.496ms)

----------------------------------------------------
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0 andrei_g

on Oct 25, 2018 6:11 AM in reply to matsu.yu.11
Hi,

What other changes have you made to the code?

I see:
../src/config.h:70:9: error: expected declaration specifiers or '...' before string constant
printf("\nWARNING no vendor defined in config.h (for carrier)\n");
https://github.com/analogdevicesinc/no-OS/blob/master/fmcdaq2/config.h#L69

The in the make flow the XILINX, ZYNQ... are predefined https://github.com/analogdevicesinc/no-OS/blob/master/scripts/zynq.mk#L39

There is something wrong with your build.

See: https://wiki.analog.com/resources/fpga/quick_validation

Andrei
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0 andrei_g

on Oct 25, 2018 6:15 AM in reply to andrei_g
Try not to use DEBUG, there will be conflicts with some xilinx files.

Andrei
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0 matsu.yu.11
on Oct 29, 2018 4:46 AM in reply to andrei_g
Hi，Andrei

I changed sin_lut in dac_buffer.c and changed DMA_BUFFER in fmcdaq 2.c from 0 to 1.

Other programs have not changed anything.
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0 matsu.yu.11
on Oct 29, 2018 4:46 AM in reply to andrei_g
Hi，Andrei

I changed sin_lut in dac_buffer.c and changed DMA_BUFFER in fmcdaq 2.c from 0 to 1.

Other programs have not changed anything.
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0 matsu.yu.11

on Oct 29, 2018 7:13 AM in reply to matsu.yu.11

As mentioned above, after changing the program, I ran make again in the Linux environment.
However, there is an error in the attached file.
If you run make run in this state, noise will be output.
How can I solve it?

Building '/sw'                                                                  
20:04:00 **** Build of configuration Release for project sw ****                
make all 
make[1]: ディレクトリ '/home/aoyagi/adi_2/no-OS/fmcdaq2/vc707/sw/Release' に入ります
Building file: ../src/ad9144.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/ad9144.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/ad9144.d" -MT"src/ad9144.o" -o "src/ad9144.o" "../src/ad9144.c"
../src/ad9144.c: In function 'ad9144_short_pattern_test':                       
../src/ad9144.c:528:50: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t {aka long unsigned int}' [-Wformat=]
     printf("%s : short-pattern-test mismatch (0x%x, 0x%x 0x%x, 0x%x)!.¥n",
                                                  ^
../src/ad9144.c:528:56: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'uint32_t {aka long unsigned int}' [-Wformat=]
     printf("%s : short-pattern-test mismatch (0x%x, 0x%x 0x%x, 0x%x)!.¥n",
                                                        ^
../src/ad9144.c:528:61: warning: format '%x' expects argument of type 'unsigned int', but argument 5 has type 'uint32_t {aka const long unsigned int}' [-Wformat=]
     printf("%s : short-pattern-test mismatch (0x%x, 0x%x 0x%x, 0x%x)!.¥n",
                                                             ^
Finished building: ../src/ad9144.c                                              
 
Building file: ../src/ad9523.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/ad9523.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/ad9523.d" -MT"src/ad9523.o" -o "src/ad9523.o" "../src/ad9523.c"
../src/ad9523.c: In function 'ad9523_calibrate':                                
../src/ad9523.c:234:44: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'uint32_t {aka long unsigned int}' [-Wformat=]
   printf("AD9523: VCO calibration failed (%x)!¥n", reg_data);
                                            ^
../src/ad9523.c: In function 'ad9523_status':
../src/ad9523.c:286:40: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'uint32_t {aka long unsigned int}' [-Wformat=]
   printf("AD9523: VCXO status errors (%x)!¥n", reg_data);
                                        ^
../src/ad9523.c:290:37: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'uint32_t {aka long unsigned int}' [-Wformat=]
   printf("AD9523: PLL2 NOT locked (%x)!¥n", reg_data);
                                     ^
../src/ad9523.c: In function 'ad9523_setup':
../src/ad9523.c:471:47: warning: format '%X' expects argument of type 'unsigned int', but argument 2 has type 'uint32_t {aka long unsigned int}' [-Wformat=]
   printf("AD9523: SPI write-verify failed (0x%X)!¥n¥r",
                                               ^
Finished building: ../src/ad9523.c                                              
 
Building file: ../src/ad9680.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/ad9680.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/ad9680.d" -MT"src/ad9680.o" -o "src/ad9680.o" "../src/ad9680.c"
Finished building: ../src/ad9680.c                                              
 
Building file: ../src/adc_core.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/adc_core.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/adc_core.d" -MT"src/adc_core.o" -o "src/adc_core.o" "../src/adc_core.c"
Finished building: ../src/adc_core.c                                            
 
Building file: ../src/altera_a10_atx_pll.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/altera_a10_atx_pll.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/altera_a10_atx_pll.d" -MT"src/altera_a10_atx_pll.o" -o "src/altera_a10_atx_pll.o" "../src/altera_a10_atx_pll.c"
Finished building: ../src/altera_a10_atx_pll.c                                  
 
Building file: ../src/altera_a10_fpll.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/altera_a10_fpll.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/altera_a10_fpll.d" -MT"src/altera_a10_fpll.o" -o "src/altera_a10_fpll.o" "../src/altera_a10_fpll.c"
Finished building: ../src/altera_a10_fpll.c                                     
 
Building file: ../src/altera_a10_xcvr_channel.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/altera_a10_xcvr_channel.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/altera_a10_xcvr_channel.d" -MT"src/altera_a10_xcvr_channel.o" -o "src/altera_a10_xcvr_channel.o" "../src/altera_a10_xcvr_channel.c"
Finished building: ../src/altera_a10_xcvr_channel.c                             
 
Building file: ../src/altera_pll_common.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/altera_pll_common.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/altera_pll_common.d" -MT"src/altera_pll_common.o" -o "src/altera_pll_common.o" "../src/altera_pll_common.c"
Finished building: ../src/altera_pll_common.c                                   
 
Building file: ../src/dac_buffer.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/dac_buffer.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/dac_buffer.d" -MT"src/dac_buffer.o" -o "src/dac_buffer.o" "../src/dac_buffer.c"
Finished building: ../src/dac_buffer.c                                          
 
Building file: ../src/dac_core.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/dac_core.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/dac_core.d" -MT"src/dac_core.o" -o "src/dac_core.o" "../src/dac_core.c"
Finished building: ../src/dac_core.c                                            
 
Building file: ../src/dmac_core.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/dmac_core.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/dmac_core.d" -MT"src/dmac_core.o" -o "src/dmac_core.o" "../src/dmac_core.c"
Finished building: ../src/dmac_core.c                                           
 
Building file: ../src/fmcdaq2.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/fmcdaq2.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/fmcdaq2.d" -MT"src/fmcdaq2.o" -o "src/fmcdaq2.o" "../src/fmcdaq2.c"
Finished building: ../src/fmcdaq2.c                                             
 
Building file: ../src/jesd_core.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/jesd_core.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/jesd_core.d" -MT"src/jesd_core.o" -o "src/jesd_core.o" "../src/jesd_core.c"
Finished building: ../src/jesd_core.c                                           
 
Building file: ../src/platform.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/platform.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c"
Finished building: ../src/platform.c
 
Building file: ../src/platform_drivers.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/platform_drivers.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform_drivers.d" -MT"src/platform_drivers.o" -o "src/platform_drivers.o" "../src/platform_drivers.c"
Finished building: ../src/platform_drivers.c                                    
 
Building file: ../src/xcvr_core.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/xcvr_core.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/xcvr_core.d" -MT"src/xcvr_core.o" -o "src/xcvr_core.o" "../src/xcvr_core.c"
Finished building: ../src/xcvr_core.c                                           
 
Building file: ../src/xilinx_qpll.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/xilinx_qpll.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/xilinx_qpll.d" -MT"src/xilinx_qpll.o" -o "src/xilinx_qpll.o" "../src/xilinx_qpll.c"
Finished building: ../src/xilinx_qpll.c                                         
 
Building file: ../src/xilinx_xcvr_channel.c
Invoking: MicroBlaze gcc compiler
mb-gcc -DXILINX -DMICROBLAZE -Wall -O2 -c -fmessage-length=0 -MT"src/xilinx_xcvr_channel.o" -I../../bsp/sys_mb/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/xilinx_xcvr_channel.d" -MT"src/xilinx_xcvr_channel.o" -o "src/xilinx_xcvr_channel.o" "../src/xilinx_xcvr_channel.c"
Finished building: ../src/xilinx_xcvr_channel.c                                 
 
Building target: sw.elf
Invoking: MicroBlaze gcc linker
mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../bsp/sys_mb/lib -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-soft-div -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high -Wl,--no-relax -Wl,--gc-sections -o "sw.elf"  ./src/ad9144.o ./src/ad9523.o ./src/ad9680.o ./src/adc_core.o ./src/altera_a10_atx_pll.o ./src/altera_a10_fpll.o ./src/altera_a10_xcvr_channel.o ./src/altera_pll_common.o ./src/dac_buffer.o ./src/dac_core.o ./src/dmac_core.o ./src/fmcdaq2.o ./src/jesd_core.o ./src/platform.o ./src/platform_drivers.o ./src/xcvr_core.o ./src/xilinx_qpll.o ./src/xilinx_xcvr_channel.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
Finished building target: sw.elf
 
Invoking: MicroBlaze Print Size
mb-size sw.elf  |tee "sw.elf.size"
   text	   data	    bss	    dec	    hex	filename
  92396	   1672	   3172	  97240	  17bd8	sw.elf
Finished building: sw.elf.size
 
make[1]: ディレクトリ '/home/aoyagi/adi_2/no-OS/fmcdaq2/vc707/sw/Release' から出ます

20:04:04 Build Finished (took 3s.994ms)

0 andrei_g

on Oct 29, 2018 9:21 AM in reply to matsu.yu.11
Hi,

Please post the UART messages here too.
Some checkpoints:
1. We have to make sure the JESD link is up. (UART messages).
2 Use the default sine_lut table, what results do you get?
3 Use your lut table, results?

Andrei
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0 matsu.yu.11

on Oct 29, 2018 10:01 PM in reply to andrei_g

Hi, Andrei

I tried both of them. The results are shown below. The same error occurred in both cases.

⑴ default sine_lut table

Available sampling rates:
	1 - ADC 1000 MSPS; DAC 1000 MSPS
	2 - ADC  500 MSPS; DAC 1000 MSPS
	3 - ADC  500 MSPS; DAC  500 MSPS
	4 - ADC  600 MSPS; DAC  600 MSPS
choose an option [default 1]:
3 - ADC  500 MSPS; DAC  500 MSPS

CPLL ENABLE
xcvr_setup ERROR: XCVR initialization failed!

CPLL ENABLE
xcvr_setup ERROR: XCVR initialization failed!
Tx link is disabled
Measured Link Clock: off
External reset is deasserted
Rx link is disabled
Measured Link Clock: off
External reset is deasserted
adc_setup adc core Status errors.
dac_setup DAC Core Status errors.

⑵ my lut table (square)

Available sampling rates:
	1 - ADC 1000 MSPS; DAC 1000 MSPS
	2 - ADC  500 MSPS; DAC 1000 MSPS
	3 - ADC  500 MSPS; DAC  500 MSPS
	4 - ADC  600 MSPS; DAC  600 MSPS
choose an option [default 1]:
3 - ADC  500 MSPS; DAC  500 MSPS

CPLL ENABLE
xcvr_setup ERROR: XCVR initialization failed!

CPLL ENABLE
xcvr_setup ERROR: XCVR initialization failed!
Tx link is disabled
Measured Link Clock: off
External reset is deasserted
Rx link is disabled
Measured Link Clock: off
External reset is deasserted
adc_setup adc core Status errors.
dac_setup DAC Core Status errors.

0 andrei_g

on Oct 30, 2018 3:12 AM in reply to matsu.yu.11
Hi,

Your problem starts here "xcvr_setup ERROR: XCVR initialization failed!"
When you first started using the reference design, did it work for you?
Have you made changes to the hardware or software regarding ad9523 or other changes that may affect the clocks in the system?
Can you create another workspace to make sure you don't have any changes affecting the functionality?
Is the board properly inserted in the FMC HPC1?

Andrei
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0 matsu.yu.11

on Oct 30, 2018 4:55 AM in reply to andrei_g

Hi, Andrei.

Thank you for reply.

https://ez.analog.com/fpga/f/q-a/101433/ad-fmcdaq2-ebz-on-vc707-problem

As a result of debugging with SDK, referring to this question, it became as follows.

Available sampling rates:
	1 - ADC 1000 MSPS; DAC 1000 MSPS
	2 - ADC  500 MSPS; DAC 1000 MSPS
	3 - ADC  500 MSPS; DAC  500 MSPS
	4 - ADC  600 MSPS; DAC  600 MSPS
choose an option [default 1]:
3 - ADC  500 MSPS; DAC  500 MSPS

CPLL ENABLE

CPLL ENABLE
Tx link is enabled
Measured Link Clock: 125 MHz
Link status: DATA
SYSREF captured: Yes
Rx link is enabled
Measured Link Clock: 125 MHz
Link status: DATA
SYSREF captured: Yes
adc_setup adc core initialized (500 MHz).
dac_setup dac core initialized (500 MHz).
daq2: transmit data from memory
daq2: RX capture done.

I think that it is working properly.

But, Looking at the output waveform it looked like the figure below.

How can I correctly output a square wave? please tell me.

my lut :

static const uint16_t sine_lut[1024] = {
	    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
		0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
	    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
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		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,
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		0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF,0x7FFF};

0 matsu.yu.11
on Oct 30, 2018 5:15 AM in reply to matsu.yu.11
Also, is it possible to make the rectangular wave V_Low 0 V, V_High 500 mV possible?
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0 andrei_g

on Oct 30, 2018 5:42 AM in reply to matsu.yu.11
What was the problem? You where using the master?

As I mentioned in the first post, the output on the DAC goes through some filters.
Ex looking at the board out 1 goes through T3... T12.
Daq2 was designing for RF, high-speed data (sine waves).
For your particular case, you have to make changes in the hardware.

Andrei
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0 matsu.yu.11
on Nov 8, 2018 3:51 AM in reply to andrei_g
Hi，

I use hdl_2018_r1 for hdl and 2018_R1 for no-OS.

I could output rectangular wave.

However, I would like to output a rectangular wave between 1 kHz and 10 kHz.
How can I implement it by changing fmcdaq2.c?
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0 andrei_g

on Nov 8, 2018 7:51 AM in reply to matsu.yu.11
Hi,

Again, why don't you simply use a GPIO not the daq2 for that?
A few ideas:

1. You can use the software to toggle a register or send/change a value at your desired frequency.
2. Use the software to write values directly in an HDL register(that you add), in the register map, as an example see dac_data_select_s (0x4418 REG_CHAN_CNTRL_7),

Feed it to the data select multiplexer https://github.com/analogdevicesinc/hdl/blob/hdl_2018_r1/library/axi_ad9144/axi_ad9144_channel.v#L269

3. Write in HDL something like:

input [31: 0] increment //from the regmap

reg [15:0] square_wave = 0;

always @(pesedge clk) begin
sawtooth_wave <= sawtooth_wave + increment;

square_wave <= {16{sawtooth_wave[31]}}
end

The frequency of your square wave is core _clock/(2^32 * increment)
use the above to calculate the value for increment.

https://en.wikipedia.org/wiki/Numerically_controlled_oscillator

You get the idea, output that trough the multiplexer mentioned above.

Andrei
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0 matsu.yu.11

on Nov 11, 2018 1:49 AM in reply to andrei_g

Hi, Thank you for your reply.

I could understand what you said.

However, I wanted to see the example ( dac_data_select_s (0x4418 REG_CHAN_CNTRL_7),) and I looked for it, but I could not find it.

Where is it?

Also, as described in the attached file, is it correct by adding the description of HDL （Number 3 of a few ideas） to axi_ad 9144_channnel.v and changing the multiplexer description to dac_data_sel_s == 4'h3 and 4'h3: dac_data <= square_wave; ? （from L266 toL290）

// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
//   1. The GNU General Public License version 2 as published by the
//      Free Software Foundation, which can be found in the top level directory
//      of this repository (LICENSE_GPL2), and also online at:
//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
//   2. An ADI specific BSD license, which can be found in the top level directory
//      of this repository (LICENSE_ADIBSD), and also on-line at:
//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
//      This will allow to generate bit files and not release the source code,
//      as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module axi_ad9144_channel #(

  parameter CHANNEL_ID = 32'h0,
  parameter DATAPATH_DISABLE = 0) (

  // dac interface

  input                   dac_clk,
  input                   dac_rst,
  output  reg             dac_enable,
  output  reg [63:0]      dac_data,
  input       [63:0]      dma_data,

  // processor interface

  input                   dac_data_sync,
  input                   dac_dds_format,

  // bus interface

  input                   up_rstn,
  input                   up_clk,
  input                   up_wreq,
  input       [13:0]      up_waddr,
  input       [31:0]      up_wdata,
  output                  up_wack,
  input                   up_rreq,
  input       [13:0]      up_raddr,
  output      [31:0]      up_rdata,
  output                  up_rack);

  

  // internal registers

  reg     [63:0]  dac_pn7_data = 'd0;
  reg     [63:0]  dac_pn15_data = 'd0;
  reg     [15:0]  dac_dds_phase_0_0 = 'd0;
  reg     [15:0]  dac_dds_phase_0_1 = 'd0;
  reg     [15:0]  dac_dds_phase_1_0 = 'd0;
  reg     [15:0]  dac_dds_phase_1_1 = 'd0;
  reg     [15:0]  dac_dds_phase_2_0 = 'd0;
  reg     [15:0]  dac_dds_phase_2_1 = 'd0;
  reg     [15:0]  dac_dds_phase_3_0 = 'd0;
  reg     [15:0]  dac_dds_phase_3_1 = 'd0;
  reg     [15:0]  dac_dds_incr_0 = 'd0;
  reg     [15:0]  dac_dds_incr_1 = 'd0;
  reg     [63:0]  dac_dds_data = 'd0;

 

  // internal signals

  wire    [15:0]  dac_dds_data_0_s;
  wire    [15:0]  dac_dds_data_1_s;
  wire    [15:0]  dac_dds_data_2_s;
  wire    [15:0]  dac_dds_data_3_s;
  wire    [15:0]  dac_dds_scale_1_s;
  wire    [15:0]  dac_dds_init_1_s;
  wire    [15:0]  dac_dds_incr_1_s;
  wire    [15:0]  dac_dds_scale_2_s;
  wire    [15:0]  dac_dds_init_2_s;
  wire    [15:0]  dac_dds_incr_2_s;
  wire    [15:0]  dac_pat_data_1_s;
  wire    [15:0]  dac_pat_data_2_s;
  wire    [ 3:0]  dac_data_sel_s;
  wire    [63:0]  dac_pn7_data_i_s;
  wire    [63:0]  dac_pn15_data_i_s;
  wire    [63:0]  dac_pn7_data_s;
  wire    [63:0]  dac_pn15_data_s;

   // PN7 function

  function [63:0] pn7;
    input [7:0] din;
    reg   [63:0] dout;
    begin
      dout[15] = din[ 6] ^ din[ 5];
      dout[14] = din[ 5] ^ din[ 4];
      dout[13] = din[ 4] ^ din[ 3];
      dout[12] = din[ 3] ^ din[ 2];
      dout[11] = din[ 2] ^ din[ 1];
      dout[10] = din[ 1] ^ din[ 0];
      dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5];
      dout[ 8] = din[ 6] ^ din[ 4];
      dout[ 7] = din[ 5] ^ din[ 3];
      dout[ 6] = din[ 4] ^ din[ 2];
      dout[ 5] = din[ 3] ^ din[ 1];
      dout[ 4] = din[ 2] ^ din[ 0];
      dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5];
      dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4];
      dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
      dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
      dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
      dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
      dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5];
      dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4];
      dout[27] = din[ 0] ^ din[ 6] ^ din[ 3];
      dout[26] = din[ 6] ^ din[ 2];
      dout[25] = din[ 5] ^ din[ 1];
      dout[24] = din[ 4] ^ din[ 0];
      dout[23] = din[ 3] ^ din[ 6] ^ din[ 5];
      dout[22] = din[ 2] ^ din[ 5] ^ din[ 4];
      dout[21] = din[ 1] ^ din[ 4] ^ din[ 3];
      dout[20] = din[ 0] ^ din[ 3] ^ din[ 2];
      dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
      dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
      dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
      dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4];
      dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3];
      dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2];
      dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1];
      dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
      dout[43] = din[ 1] ^ din[ 3] ^ din[ 6];
      dout[42] = din[ 0] ^ din[ 5] ^ din[ 2];
      dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1];
      dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0];
      dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5];
      dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4];
      dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3];
      dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2];
      dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1];
      dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0];
      dout[33] = din[ 0] ^ din[ 2] ^ din[ 6];
      dout[32] = din[ 6] ^ din[ 1];
      dout[63] = din[ 5] ^ din[ 0];
      dout[62] = din[ 4] ^ din[ 6] ^ din[ 5];
      dout[61] = din[ 3] ^ din[ 5] ^ din[ 4];
      dout[60] = din[ 2] ^ din[ 4] ^ din[ 3];
      dout[59] = din[ 1] ^ din[ 3] ^ din[ 2];
      dout[58] = din[ 0] ^ din[ 2] ^ din[ 1];
      dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0];
      dout[56] = din[ 0] ^ din[ 4] ^ din[ 6];
      dout[55] = din[ 6] ^ din[ 3];
      dout[54] = din[ 5] ^ din[ 2];
      dout[53] = din[ 4] ^ din[ 1];
      dout[52] = din[ 3] ^ din[ 0];
      dout[51] = din[ 2] ^ din[ 6] ^ din[ 5];
      dout[50] = din[ 1] ^ din[ 5] ^ din[ 4];
      dout[49] = din[ 0] ^ din[ 4] ^ din[ 3];
      dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2];
      pn7 = dout;
    end
  endfunction
  
  // PN15 function

  function [63:0] pn15;
    input [15:0] din;
    reg   [63:0] dout;
    begin
      dout[15] = din[14] ^ din[13];
      dout[14] = din[13] ^ din[12];
      dout[13] = din[12] ^ din[11];
      dout[12] = din[11] ^ din[10];
      dout[11] = din[10] ^ din[ 9];
      dout[10] = din[ 9] ^ din[ 8];
      dout[ 9] = din[ 8] ^ din[ 7];
      dout[ 8] = din[ 7] ^ din[ 6];
      dout[ 7] = din[ 6] ^ din[ 5];
      dout[ 6] = din[ 5] ^ din[ 4];
      dout[ 5] = din[ 4] ^ din[ 3];
      dout[ 4] = din[ 3] ^ din[ 2];
      dout[ 3] = din[ 2] ^ din[ 1];
      dout[ 2] = din[ 1] ^ din[ 0];
      dout[ 1] = din[ 0] ^ din[14] ^ din[13];
      dout[ 0] = din[14] ^ din[12];
      dout[31] = din[13] ^ din[11];
      dout[30] = din[12] ^ din[10];
      dout[29] = din[11] ^ din[ 9];
      dout[28] = din[10] ^ din[ 8];
      dout[27] = din[ 9] ^ din[ 7];
      dout[26] = din[ 8] ^ din[ 6];
      dout[25] = din[ 7] ^ din[ 5];
      dout[24] = din[ 6] ^ din[ 4];
      dout[23] = din[ 5] ^ din[ 3];
      dout[22] = din[ 4] ^ din[ 2];
      dout[21] = din[ 3] ^ din[ 1];
      dout[20] = din[ 2] ^ din[ 0];
      dout[19] = din[ 1] ^ din[14] ^ din[13];
      dout[18] = din[ 0] ^ din[13] ^ din[12];
      dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11];
      dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10];
      dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
      dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
      dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
      dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
      dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
      dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
      dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
      dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
      dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
      dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
      dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13];
      dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12];
      dout[35] = din[ 0] ^ din[14] ^ din[11];
      dout[34] = din[14] ^ din[10];
      dout[33] = din[13] ^ din[ 9];
      dout[32] = din[12] ^ din[ 8];
      dout[63] = din[11] ^ din[ 7];
      dout[62] = din[10] ^ din[ 6];
      dout[61] = din[ 9] ^ din[ 5];
      dout[60] = din[ 8] ^ din[ 4];
      dout[59] = din[ 7] ^ din[ 3];
      dout[58] = din[ 6] ^ din[ 2];
      dout[57] = din[ 5] ^ din[ 1];
      dout[56] = din[ 4] ^ din[ 0];
      dout[55] = din[ 3] ^ din[14] ^ din[13];
      dout[54] = din[ 2] ^ din[13] ^ din[12];
      dout[53] = din[ 1] ^ din[12] ^ din[11];
      dout[52] = din[ 0] ^ din[11] ^ din[10];
      dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9];
      dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8];
      dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7];
      dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6];
      pn15 = dout;
    end
  endfunction

  assign dac_pn7_data_i_s  = ~dac_pn7_data;
  assign dac_pn15_data_i_s = ~dac_pn15_data;

  assign dac_pn7_data_s    = dac_pn7_data;
  assign dac_pn15_data_s   = dac_pn15_data;




  //my scripts
  
  input       [31:0]      increment,
  reg [15:0] square_wave = 0;
  
  always @(pesedge clk)begin
    sawtooth_wave <= sawtooth_wave + increment;
    square_wave <= {16{sawtooth_wave[31]}}
  end
  // dac data select

  always @(posedge dac_clk) begin
    dac_enable <= (dac_data_sel_s == 4'h3) ? 1'b1 : 1'b0;
    case (dac_data_sel_s)
      4'h7: dac_data <= dac_pn15_data_s;
      4'h6: dac_data <= dac_pn7_data_s;
      4'h5: dac_data <= dac_pn15_data_i_s;
      4'h4: dac_data <= dac_pn7_data_i_s;
      4'h3: dac_data <= square_wave;
      4'h2: dac_data <= dma_data;
      4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
                          dac_pat_data_2_s, dac_pat_data_1_s};
      default: dac_data <= dac_dds_data;
    endcase
  end
  
  

  // pn registers

  always @(posedge dac_clk) begin
    if (dac_data_sync == 1'b1) begin
      dac_pn7_data <= {64{1'd1}};
      dac_pn15_data <= {64{1'd1}};
    end else begin
      dac_pn7_data <= pn7(dac_pn7_data[55:48]);
      dac_pn15_data <= pn15(dac_pn15_data[63:48]);
    end
  end

  // dds

  always @(posedge dac_clk) begin
    if (dac_data_sync == 1'b1) begin
      dac_dds_phase_0_0 <= dac_dds_init_1_s;
      dac_dds_phase_0_1 <= dac_dds_init_2_s;
      dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
      dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
      dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
      dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
      dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
      dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
      dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0};
      dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0};
      dac_dds_data <= 64'd0;
    end else begin
      dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
      dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
      dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
      dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
      dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
      dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
      dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
      dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
      dac_dds_incr_0 <= dac_dds_incr_0;
      dac_dds_incr_1 <= dac_dds_incr_1;
      dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s,
                        dac_dds_data_1_s, dac_dds_data_0_s};
    end
  end

  generate
  if (DATAPATH_DISABLE == 1) begin
  assign dac_dds_data_0_s = 16'd0;
  end else begin
  ad_dds i_dds_0 (
    .clk (dac_clk),
    .dds_format (dac_dds_format),
    .dds_phase_0 (dac_dds_phase_0_0),
    .dds_scale_0 (dac_dds_scale_1_s),
    .dds_phase_1 (dac_dds_phase_0_1),
    .dds_scale_1 (dac_dds_scale_2_s),
    .dds_data (dac_dds_data_0_s));
  end
  endgenerate
  
  generate
  if (DATAPATH_DISABLE == 1) begin
  assign dac_dds_data_1_s = 16'd0;
  end else begin
  ad_dds i_dds_1 (
    .clk (dac_clk),
    .dds_format (dac_dds_format),
    .dds_phase_0 (dac_dds_phase_1_0),
    .dds_scale_0 (dac_dds_scale_1_s),
    .dds_phase_1 (dac_dds_phase_1_1),
    .dds_scale_1 (dac_dds_scale_2_s),
    .dds_data (dac_dds_data_1_s));
  end
  endgenerate
  
  generate
  if (DATAPATH_DISABLE == 1) begin
  assign dac_dds_data_2_s = 16'd0;
  end else begin
  ad_dds i_dds_2 (
    .clk (dac_clk),
    .dds_format (dac_dds_format),
    .dds_phase_0 (dac_dds_phase_2_0),
    .dds_scale_0 (dac_dds_scale_1_s),
    .dds_phase_1 (dac_dds_phase_2_1),
    .dds_scale_1 (dac_dds_scale_2_s),
    .dds_data (dac_dds_data_2_s));
  end
  endgenerate
  
  generate
  if (DATAPATH_DISABLE == 1) begin
  assign dac_dds_data_3_s = 16'd0;
  end else begin
  ad_dds i_dds_3 (
    .clk (dac_clk),
    .dds_format (dac_dds_format),
    .dds_phase_0 (dac_dds_phase_3_0),
    .dds_scale_0 (dac_dds_scale_1_s),
    .dds_phase_1 (dac_dds_phase_3_1),
    .dds_scale_1 (dac_dds_scale_2_s),
    .dds_data (dac_dds_data_3_s));
  end
  endgenerate
  
  // single channel processor

  up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
    .dac_clk (dac_clk),
    .dac_rst (dac_rst),
    .dac_dds_scale_1 (dac_dds_scale_1_s),
    .dac_dds_init_1 (dac_dds_init_1_s),
    .dac_dds_incr_1 (dac_dds_incr_1_s),
    .dac_dds_scale_2 (dac_dds_scale_2_s),
    .dac_dds_init_2 (dac_dds_init_2_s),
    .dac_dds_incr_2 (dac_dds_incr_2_s),
    .dac_pat_data_1 (dac_pat_data_1_s),
    .dac_pat_data_2 (dac_pat_data_2_s),
    .dac_data_sel (dac_data_sel_s),
    .dac_iq_mode (),
    .dac_iqcor_enb (),
    .dac_iqcor_coeff_1 (),
    .dac_iqcor_coeff_2 (),
    .up_usr_datatype_be (),
    .up_usr_datatype_signed (),
    .up_usr_datatype_shift (),
    .up_usr_datatype_total_bits (),
    .up_usr_datatype_bits (),
    .up_usr_interpolation_m (),
    .up_usr_interpolation_n (),
    .dac_usr_datatype_be (1'b0),
    .dac_usr_datatype_signed (1'b1),
    .dac_usr_datatype_shift (8'd0),
    .dac_usr_datatype_total_bits (8'd16),
    .dac_usr_datatype_bits (8'd16),
    .dac_usr_interpolation_m (16'd1),
    .dac_usr_interpolation_n (16'd1),
    .up_rstn (up_rstn),
    .up_clk (up_clk),
    .up_wreq (up_wreq),
    .up_waddr (up_waddr),
    .up_wdata (up_wdata),
    .up_wack (up_wack),
    .up_rreq (up_rreq),
    .up_raddr (up_raddr),
    .up_rdata (up_rdata),
    .up_rack (up_rack));
  
endmodule

// ***************************************************************************
// ***************************************************************************

Please teach me.