Arria10 AD9371: Bad Tx frame sent from SW when Rx/Tx sampling rates differ

dglee

on Oct 9, 2018

Hello. I am currently using the Qsys ADRV9371 reference design for the 2017 R1 branch.

I am also using the patch for the DMA IP core to fix an issue where pushing a single buffer always resulted in cyclic transmit behavior. This fix was described here:

https://ez.analog.com/linux-device-drivers/linux-software-drivers/f/q-a/90807/arria10-ad9371-iio_push_buffer-always-gives-cyclic-transmit-behavior

I am also using the latest Arria10 Linux ADI drivers from 2017 R1.

The problem I am seeing is that when I push an IIO buffer (cyclic or non-cyclic, both cases) when Tx and Rx sampling rates are different I see corruption in the frame where the data is zero sometimes. This was tested with the default rates of 254.76 and 122.88 MHz respectively for Tx and Rx. I confirmed this by using the BIST loopback mode (Tx->Rx digital loopback) and was not transmitting over analog. I am receiving the data by using IIO calls to define the buffer size (iio_device_create_buffer). On the PL I am commanding a data capture routine by specifying how many clock-cycles to capture data for through using the valid signals entering the CPACK IP core.

Here is an example where I push a TX ramp counter from 1 to 2^15. Most ramps come through fine but then sometimes I will see drops in samples.

The plot was generated using the iio_refill_buffer on the Rx side. The receiver is not overflowing. I command the PL over AXI4 to capture a configurable number of samples that matches the number of samples set by the IIO l buffer API call such that I can control exactly how many frames I get. Another test I did was with DDS which works fine - by using the same AXI4 data capture triggering mechanism, I was able to receive a full un-corrupted frame from a DDS BIST loopback. Based on the testing above, i believe there is some drop in data happening on the TX-DMA data pathside.

If I set the base-band sample rates for Tx and Rx to match exactly this problem is no longer observed. I have tested this by setting the rates to be 61.44 MHz for both Tx and Rx. This config file is attached.

Fullscreen 61_44_profile.txt Download

<profile AD9371 version=0 name=Rx 50, IQrate 61.440>
 <clocks>
  <deviceClock_kHz=76800>
  <clkPllVcoFreq_kHz=9830400>
  <clkPllVcoDiv=2>
  <clkPllHsDiv=4>
 </clocks>

 <rx>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=61440>
  <rfBandwidth_Hz=50000000>
  <rxBbf3dBCorner_kHz=50000>

  <filter FIR gain=-6 num=72>
  0
  -1
  2
  3
  -5
  -7
  11
  15
  -23
  -29
  43
  54
  -75
  -92
  125
  150
  -198
  -235
  302
  355
  -447
  -524
  646
  759
  -920
  -1089
  1302
  1568
  -1864
  -2324
  2763
  3696
  -4513
  -7179
  9583
  31418
  31418
  9583
  -7179
  -4513
  3696
  2763
  -2324
  -1864
  1568
  1302
  -1089
  -920
  759
  646
  -524
  -447
  355
  302
  -235
  -198
  150
  125
  -92
  -75
  54
  43
  -29
  -23
  15
  11
  -7
  -5
  3
  2
  -1
  0
  </filter>

  <adc-profile num=16>
  596
  358
  201
  98
  1280
  134
  1509
  64
  1329
  25
  818
  39
  48
  40
  23
  190
  </adc-profile>
 </rx>

 <obs>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=61440>
  <rfBandwidth_Hz=40000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=72>
  3
  2
  -8
  -10
  8
  30
  6
  -52
  -51
  55
  127
  1
  -206
  -147
  216
  375
  -63
  -596
  -319
  639
  889
  -296
  -1445
  -570
  1618
  1893
  -951
  -3304
  -968
  4064
  4403
  -2936
  -9821
  -4360
  14179
  31305
  31305
  14179
  -4360
  -9821
  -2936
  4403
  4064
  -968
  -3304
  -951
  1893
  1618
  -570
  -1445
  -296
  889
  639
  -319
  -596
  -63
  375
  216
  -147
  -206
  1
  127
  55
  -51
  -52
  6
  30
  8
  -10
  -8
  2
  3
  </filter>

  <adc-profile num=16>
  599
  357
  201
  98
  1280
  112
  1505
  53
  1331
  21
  820
  40
  48
  40
  23
  191
  </adc-profile>

  <lpbk-adc-profile num=16>
  599
  357
  201
  98
  1280
  112
  1505
  53
  1331
  21
  820
  40
  48
  40
  23
  191
  </lpbk-adc-profile>
 </obs>

 <tx>
  <dacDiv=2.5>
  <txFirInterpolation=2>
  <thb1Interpolation=2>
  <thb2Interpolation=2>
  <txInputHbInterpolation=1>
  <iqRate_kHz=61440>
  <primarySigBandwidth_Hz=20000000>
  <rfBandwidth_Hz=40000000>
  <txDac3dBCorner_kHz=92000>
  <txBbf3dBCorner_kHz=20000>

  <filter FIR gain=0 num=32>
  -11
  -15
  58
  78
  -190
  -264
  475
  693
  -1024
  -1644
  1893
  3779
  -2438
  -7373
  2905
  19451
  19451
  2905
  -7373
  -2438
  3779
  1893
  -1644
  -1024
  693
  475
  -264
  -190
  78
  58
  -15
  -11
  </filter>
 </tx>
</profile>

Is it recommended to use the same base-band sampling rates for Tx and Rx when pushing a buffer out from software?

Parents

+1 ADIApproved

on Oct 10, 2018 2:38 AM
Hi,

I recommend using the 2018_r1 branch instead of 2017_r1. An issue with similar behavior is fixed in 2018_r1 by this commit.

Having separate Rx and Tx rates should not be a problem.

Laszlo
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0 dglee
on Nov 9, 2018 9:20 AM in reply to ADIApproved
Hello,

I have tried the 2018 (hdl_2018_r1 git-hash d79ca23528 to be exact) branch and unfortunately I get the same error from the A10 SoC Quartus project. To re-iterate, the test I am doing is pushing out a known Tx frame out, enabling BIST loopback and examining the Rx data path with differing sample rates. Zeros appear in the Rx frame as depicted previously. Here it is again for reference.

For the Tx frame, I am providing ramp signals for both I and Q with different slopes.

If i set the sample rates to be the same the problem no longer occurs (ie: 61.44 MSPS for both ADC/DAC) and the ramps appear fine. Above tests are done with cyclic mode enabled. This behavior is also seen in IIO-Oscilloscope. The IIO-Scope test was done as follows:

1) Run embedded-Linux binary that pushes a single Tx frame in cyclic mode

2) Run IIO Scope on desktop PC and examined broken Rx frame with BIST loopback enabled

It should be noted that one thing I am doing differently is using a split-bitstream (socfpga.periph.rbf and socfpga.core.rbf) approach called "Early IO Release" mode. I was able to get faster boot-times because of this. In order to support this, I modified the 2018_r1 project settings to enable this feature as well as use a modified U-boot to load the bit-streams correctly.

1) Enable "HPS ealry release of HPS IO" for the Quartus project

2) Enable HPS Early Release mode in the PS DDR4 IP property

3) I am also making use of additional AXI buses from the HPs

This creates additional AXI4 Master/Slave connections to the HPS but they route to other IP cores that do not really interact directly the AD9371 IP.

I don't believe this should impact the behavior here but it might be worth noting.

Question: I am still using the same Linux as stated above, when using the 2018 ADI-HDL branch, does that matter? Should I be incorporating more kernel driver updates than the one I am currently on? (see first post in this thread).

I would like to add one more comment on something that I just noticed:

In my testing for Rx and Tx, i've always set the Tx cyclic frame size to a value of 3072. The Rx frame-size however is something much larger (10K samples). If Tx and Rx sample rates do not match I see the problem. However, if I set the frame size for Rx to be exactly 3072, I do not see the samples dropping to zero. Setting the Rx frame size to something like 3072*2, the problem occurs less frequently but is still present.

On some occasions, I've noticed that the corrupt frame issue happens every 16 frames, but i'm not sure what triggers this. Maybe it relates to IIO kernel buffer depth but this is not something I'm modifying - I believe the default value is 4?

Once again, setting Tx and Rx to be the same sampling rate does not experience the same behavior.
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0 ADIApproved

on Nov 9, 2018 9:43 AM in reply to dglee
Hi.

sorry for the late reply.

Could you please share the profile you are using when you encounter the issue ? You shared just the one where the rx/tx rates match.

Do you encounter the issue with different frame sizes like power of 2 or just with 3072?

Thanks.

Laszlo
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0 dglee

on Nov 9, 2018 12:20 PM in reply to ADIApproved

For testing with the tx/rx rates do not match, I am simply using the default rates when you power up the board with the default device tree. Therefore, I did not apply a profile_config on the device. Here is the dmesg output that captures the relevant AD9371 settings

[    1.232224] altera-a10-fpll ff245000.altera-a10-fpll: FPLL PLL calibration OK (1400 us)
[    1.234131] altera-a10-fpll ff235000.altera-a10-fpll: FPLL PLL calibration OK (1400 us)
[    1.236153] altera-a10-fpll ff225000.altera-a10-fpll: FPLL PLL calibration OK (1400 us)
[    1.275209] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: ATX PLL calibration OK (20 ms)
[    1.298438] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Lane 0 TX termination and VOD calibration OK (600 us)
[    1.333594] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Lane 1 TX termination and VOD calibration OK (600 us)
[    1.349425] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Lane 2 TX termination and VOD calibration OK (600 us)
[    1.378946] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Lane 3 TX termination and VOD calibration OK (600 us)
[    1.388769] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Altera ADXCVR (16.01.a) probed
[    1.401306] altera_adxcvr ff234000.axi-ad9371-rx-xcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
[    1.415333] altera_adxcvr ff234000.axi-ad9371-rx-xcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
[    1.425228] altera_adxcvr ff234000.axi-ad9371-rx-xcvr: Altera ADXCVR (16.01.a) probed
[    1.437920] altera_adxcvr ff244000.axi-ad9371-rx-os-xcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
[    1.451858] altera_adxcvr ff244000.axi-ad9371-rx-os-xcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
[    1.462006] altera_adxcvr ff244000.axi-ad9371-rx-os-xcvr: Altera ADXCVR (16.01.a) probed
[    1.470487] fpga_manager fpga0: SoCFPGA Arria10 FPGA Manager registered
[    1.477537] oprofile: no performance counters
[    1.481984] oprofile: using timer interrupt.
[    1.486885] NET: Registered protocol family 10
[    1.491652] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Setting link rate to 122880000 (lane rate: 4915200)
[    1.501767] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    1.502327] altera_adxcvr ff234000.axi-ad9371-rx-xcvr: Setting link rate to 122880000 (lane rate: 4915200)
[    1.503341] altera_adxcvr ff244000.axi-ad9371-rx-os-xcvr: Setting link rate to 122880000 (lane rate: 4915200)
[    1.527719] NET: Registered protocol family 17
[    1.532179] NET: Registered protocol family 15
[    1.536603] can: controller area network core (rev 20120528 abi 9)
[    1.542807] NET: Registered protocol family 29
[    1.547231] can: raw protocol (rev 20120528)
[    1.551479] can: broadcast manager protocol (rev 20161123 t)
[    1.557120] can: netlink gateway (rev 20130117) max_hops=1
[    1.562764] 8021q: 802.1Q VLAN Support v1.8
[    1.566962] Key type dns_resolver registered
[    1.571266] ThumbEE CPU extension supported.
[    1.575534] Registering SWP/SWPB emulation handler
[    1.582822] ad9371 spi32766.1: ad9371_probe : enter
[    1.589113] ad9371 spi32766.1: ad9371_probe : enter
[    3.280171] random: crng init done
[   29.086754] ad9371 spi32766.1: framerStatus (0x20)
[   29.154287] ad9371 spi32766.1: ad9371_probe : AD9371 Rev 4, Firmware 5.1.1 API version: 1.5.1.3565 successfully initialized
[   29.176743] cf_axi_dds ff254000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0xFF254000 mapped to 0xf09a0000, probed DDS AD9371
[   29.210875] cf_axi_adc ff250000.axi-ad9371-rx-hpc: ADI AIM (10.00.b) at 0xFF250000 mapped to 0xf09a8000, probed ADC AD9371 as MASTER

Device tree

/dts-v1/;

/ {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	model = "Altera SOCFPGA Arria 10";
	compatible = "altr,socfpga-arria10", "altr,socfpga";

	chosen {
		bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p3 rw rootwait earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	aliases {
		ethernet0 = "/soc/ethernet@ff800000";
		serial0 = "/soc/serial1@ffc02100";
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		enable-method = "altr,socfpga-a10-smp";

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x0>;
			next-level-cache = <0x1>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x1>;
			next-level-cache = <0x1>;
		};
	};

	intc@ffffd000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <0x3>;
		interrupt-controller;
		reg = <0xffffd000 0x1000 0xffffc100 0x100>;
		linux,phandle = <0x2>;
		phandle = <0x2>;
	};

	soc {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <0x2>;
		ranges;

		amba {
			compatible = "simple-bus";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;

			pdma@ffda1000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0xffda1000 0x1000>;
				interrupts = <0x0 0x53 0x4 0x0 0x54 0x4 0x0 0x55 0x4 0x0 0x56 0x4 0x0 0x57 0x4 0x0 0x58 0x4 0x0 0x59 0x4 0x0 0x5a 0x4 0x0 0x5b 0x4>;
				#dma-cells = <0x1>;
				#dma-channels = <0x8>;
				#dma-requests = <0x20>;
				clocks = <0x3>;
				clock-names = "apb_pclk";
				microcode-cached;
				linux,phandle = <0x1b>;
				phandle = <0x1b>;
			};
		};

		base_fpga_region {
			#address-cells = <0x2>;
			#size-cells = <0x1>;
			compatible = "fpga-region", "simple-bus";
			fpga-mgr = <0x4>;
			ranges = <0x0 0x0 0xc0000000 0x20000000 0x1 0x0 0xff200000 0x200000>;

			bridge0@0x0 {
				compatible = "simple-bus";
				#size-cells = <0x1>;
				#address-cells = <0x1>;
				ranges = <0x0 0x0 0x0 0x20000000>;

				mwipcore@0x00000000 {
					status = "disabled";
					compatible = "mathworks,mwipcore-v3.00";
					reg = <0x0 0x10000>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					mmrd-channel@0 {
						status = "disabled";
						reg = <0x0>;
						compatible = "mathworks,mm-read-channel-v1.00";
						mathworks,dev-name = "mmrd0";
					};

					mmwr-channel@1 {
						status = "disabled";
						reg = <0x1>;
						compatible = "mathworks,mm-write-channel-v1.00";
						mathworks,dev-name = "mmwr0";
					};
				};
			};

			bridge1@0x1 {
				compatible = "simple-bus";
				#size-cells = <0x1>;
				#address-cells = <0x1>;
				ranges = <0x0 0x1 0x0 0x200000>;
			};
		};

		clkmgr@ffd04000 {
			compatible = "altr,clk-mgr";
			reg = <0xffd04000 0x1000>;

			clocks {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				cb_intosc_hs_div2_clk {
					#clock-cells = <0x0>;
					compatible = "fixed-clock";
					linux,phandle = <0xd>;
					phandle = <0xd>;
				};

				cb_intosc_ls_clk {
					#clock-cells = <0x0>;
					compatible = "fixed-clock";
					linux,phandle = <0x6>;
					phandle = <0x6>;
				};

				f2s_free_clk {
					#clock-cells = <0x0>;
					compatible = "fixed-clock";
					linux,phandle = <0x7>;
					phandle = <0x7>;
				};

				osc1 {
					#clock-cells = <0x0>;
					compatible = "fixed-clock";
					clock-frequency = <0x17d7840>;
					linux,phandle = <0x5>;
					phandle = <0x5>;
				};

				main_pll {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-pll-clock";
					clocks = <0x5 0x6 0x7>;
					reg = <0x40>;
					linux,phandle = <0x8>;
					phandle = <0x8>;

					main_mpu_base_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						div-reg = <0x140 0x0 0xb>;
						linux,phandle = <0xb>;
						phandle = <0xb>;
					};

					main_noc_base_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						div-reg = <0x144 0x0 0xb>;
						linux,phandle = <0xe>;
						phandle = <0xe>;
					};

					main_emaca_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x68>;
					};

					main_emacb_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x6c>;
					};

					main_emac_ptp_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x70>;
					};

					main_gpio_db_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x74>;
					};

					main_sdmmc_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x78>;
						linux,phandle = <0x12>;
						phandle = <0x12>;
					};

					main_s2f_usr0_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x7c>;
					};

					main_s2f_usr1_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x80>;
						linux,phandle = <0x10>;
						phandle = <0x10>;
					};

					main_hmc_pll_ref_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x84>;
					};

					main_periph_ref_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x9c>;
						linux,phandle = <0x9>;
						phandle = <0x9>;
					};
				};

				periph_pll {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-pll-clock";
					clocks = <0x5 0x6 0x7 0x9>;
					reg = <0xc0>;
					linux,phandle = <0xa>;
					phandle = <0xa>;

					peri_mpu_base_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						div-reg = <0x140 0x10 0xb>;
						linux,phandle = <0xc>;
						phandle = <0xc>;
					};

					peri_noc_base_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						div-reg = <0x144 0x10 0xb>;
						linux,phandle = <0xf>;
						phandle = <0xf>;
					};

					peri_emaca_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xe8>;
					};

					peri_emacb_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xec>;
					};

					peri_emac_ptp_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xf0>;
					};

					peri_gpio_db_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xf4>;
					};

					peri_sdmmc_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xf8>;
						linux,phandle = <0x13>;
						phandle = <0x13>;
					};

					peri_s2f_usr0_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xfc>;
					};

					peri_s2f_usr1_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0x100>;
						linux,phandle = <0x11>;
						phandle = <0x11>;
					};

					peri_hmc_pll_ref_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0x104>;
					};
				};

				mpu_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0xb 0xc 0x5 0xd 0x7>;
					reg = <0x60>;
					linux,phandle = <0x15>;
					phandle = <0x15>;
				};

				noc_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0xe 0xf 0x5 0xd 0x7>;
					reg = <0x64>;
					linux,phandle = <0x14>;
					phandle = <0x14>;
				};

				s2f_user1_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x10 0x11 0x5 0xd 0x7>;
					reg = <0x104>;
				};

				sdmmc_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x12 0x13 0x5 0xd 0x7>;
					fixed-divider = <0x4>;
					reg = <0xf8>;
					linux,phandle = <0x16>;
					phandle = <0x16>;
				};

				l4_sys_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x14>;
					fixed-divider = <0x4>;
					linux,phandle = <0x25>;
					phandle = <0x25>;
				};

				l4_main_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x14>;
					div-reg = <0xa8 0x0 0x2>;
					clk-gate = <0x48 0x1>;
					linux,phandle = <0x3>;
					phandle = <0x3>;
				};

				l4_mp_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x14>;
					div-reg = <0xa8 0x8 0x2>;
					clk-gate = <0x48 0x2>;
					linux,phandle = <0x17>;
					phandle = <0x17>;
				};

				l4_sp_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x14>;
					div-reg = <0xa8 0x10 0x2>;
					clk-gate = <0x48 0x3>;
					linux,phandle = <0x1a>;
					phandle = <0x1a>;
				};

				mpu_periph_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x15>;
					fixed-divider = <0x4>;
					clk-gate = <0x48 0x0>;
					linux,phandle = <0x24>;
					phandle = <0x24>;
				};

				sdmmc_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x16>;
					clk-gate = <0xc8 0x5>;
					clk-phase = <0x0 0x87>;
					linux,phandle = <0x1e>;
					phandle = <0x1e>;
				};

				qspi_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x3>;
					clk-gate = <0xc8 0xb>;
					linux,phandle = <0x23>;
					phandle = <0x23>;
				};

				nand_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x17>;
					clk-gate = <0xc8 0xa>;
					linux,phandle = <0x1f>;
					phandle = <0x1f>;
				};

				spi_m_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x3>;
					clk-gate = <0xc8 0x9>;
					linux,phandle = <0x1c>;
					phandle = <0x1c>;
				};

				usb_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x17>;
					clk-gate = <0xc8 0x8>;
					linux,phandle = <0x26>;
					phandle = <0x26>;
				};

				s2f_usr1_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x11>;
					clk-gate = <0xc8 0x6>;
				};
			};
		};

		ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <0x18 0x44 0x0>;
			reg = <0xff800000 0x2000>;
			interrupts = <0x0 0x5c 0x4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <0x100>;
			snps,perfect-filter-entries = <0x80>;
			tx-fifo-depth = <0x1000>;
			rx-fifo-depth = <0x4000>;
			clocks = <0x17>;
			clock-names = "stmmaceth";
			resets = <0x19 0x20>;
			reset-names = "stmmaceth";
			status = "okay";
			phy-mode = "rgmii";
			phy-addr = <0xffffffff>;
			txd0-skew-ps = <0x0>;
			txd1-skew-ps = <0x0>;
			txd2-skew-ps = <0x0>;
			txd3-skew-ps = <0x0>;
			rxd0-skew-ps = <0x1a4>;
			rxd1-skew-ps = <0x1a4>;
			rxd2-skew-ps = <0x1a4>;
			rxd3-skew-ps = <0x1a4>;
			txen-skew-ps = <0x0>;
			txc-skew-ps = <0x744>;
			rxdv-skew-ps = <0x1a4>;
			rxc-skew-ps = <0x690>;
			max-frame-size = <0xed8>;
			linux,phandle = <0x21>;
			phandle = <0x21>;
		};

		ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <0x18 0x48 0x0>;
			reg = <0xff802000 0x2000>;
			interrupts = <0x0 0x5d 0x4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <0x100>;
			snps,perfect-filter-entries = <0x80>;
			tx-fifo-depth = <0x1000>;
			rx-fifo-depth = <0x4000>;
			clocks = <0x17>;
			clock-names = "stmmaceth";
			resets = <0x19 0x21>;
			reset-names = "stmmaceth";
			status = "disabled";
		};

		ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <0x18 0x4c 0x0>;
			reg = <0xff804000 0x2000>;
			interrupts = <0x0 0x5e 0x4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <0x100>;
			snps,perfect-filter-entries = <0x80>;
			tx-fifo-depth = <0x1000>;
			rx-fifo-depth = <0x4000>;
			clocks = <0x17>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gpio@ffc02900 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02900 0x100>;
			status = "disabled";

			gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <0x2>;
				snps,nr-gpios = <0x1d>;
				reg = <0x0>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupts = <0x0 0x70 0x4>;
			};
		};

		gpio@ffc02a00 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02a00 0x100>;
			status = "okay";

			gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <0x2>;
				snps,nr-gpios = <0x1d>;
				reg = <0x0>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupts = <0x0 0x71 0x4>;
				linux,phandle = <0x1d>;
				phandle = <0x1d>;
			};
		};

		gpio@ffc02b00 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02b00 0x100>;
			status = "disabled";

			gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <0x2>;
				snps,nr-gpios = <0x1b>;
				reg = <0x0>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupts = <0x0 0x72 0x4>;
			};
		};

		fpga-mgr@ffd03000 {
			compatible = "altr,socfpga-a10-fpga-mgr";
			reg = <0xffd03000 0x100 0xffcfe400 0x20>;
			clocks = <0x17>;
			resets = <0x19 0x83>;
			reset-names = "fpgamgr";
			linux,phandle = <0x4>;
			phandle = <0x4>;
		};

		i2c@ffc02200 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02200 0x100>;
			interrupts = <0x0 0x69 0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		i2c@ffc02300 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02300 0x100>;
			interrupts = <0x0 0x6a 0x4>;
			clocks = <0x1a>;
			status = "okay";
			clock-frequency = <0x186a0>;
			i2c-sda-falling-time-ns = <0x1770>;
			i2c-scl-falling-time-ns = <0x1770>;

			lcd@28 {
				compatible = "newhaven,nhd-0216k3z-nsw-bbw";
				reg = <0x28>;
				height = <0x2>;
				width = <0x10>;
				brightness = <0x8>;
			};

			eeprom@51 {
				compatible = "atmel,24c32";
				reg = <0x51>;
				pagesize = <0x20>;
			};

			rtc@68 {
				compatible = "dallas,ds1339";
				reg = <0x68>;
			};

			max@4c {
				compatible = "max1619";
				reg = <0x4c>;
			};

			ltc@5c {
				compatible = "ltc2977";
				reg = <0x5c>;
			};
		};

		i2c@ffc02400 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02400 0x100>;
			interrupts = <0x0 0x6b 0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		i2c@ffc02500 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02500 0x100>;
			interrupts = <0x0 0x6c 0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		i2c@ffc02600 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02600 0x100>;
			interrupts = <0x0 0x6d 0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		spi@ffda5000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			reg = <0xffda5000 0x100>;
			interrupts = <0x0 0x66 0x4>;
			num-chipselect = <0x4>;
			bus-num = <0x0>;
			tx-dma-channel = <0x1b 0x10>;
			rx-dma-channel = <0x1b 0x11>;
			clocks = <0x1c>;
			status = "okay";

			resource-manager@0 {
				compatible = "altr,a10sr";
				reg = <0x0>;
				spi-max-frequency = <0x186a0>;
				interrupt-parent = <0x1d>;
				interrupts = <0x5 0x8>;
				interrupt-controller;
				#interrupt-cells = <0x2>;

				gpio-controller {
					compatible = "altr,a10sr-gpio";
					gpio-controller;
					#gpio-cells = <0x2>;
					linux,phandle = <0x39>;
					phandle = <0x39>;
				};

				ps_alarm {
					compatible = "altr,a10sr-hwmon";
				};
			};
		};

		sdr@ffc25000 {
			compatible = "altr,sdr-ctl", "syscon";
			reg = <0xffcfb100 0x80>;
			linux,phandle = <0x20>;
			phandle = <0x20>;
		};

		l2-cache@fffff000 {
			compatible = "arm,pl310-cache";
			reg = <0xfffff000 0x1000>;
			interrupts = <0x0 0x12 0x4>;
			cache-unified;
			cache-level = <0x2>;
			prefetch-data = <0x1>;
			prefetch-instr = <0x1>;
			arm,shared-override;
			linux,phandle = <0x1>;
			phandle = <0x1>;
		};

		dwmmc0@ff808000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0x0 0x62 0x4>;
			fifo-depth = <0x400>;
			clocks = <0x17 0x1e>;
			clock-names = "biu", "ciu";
			status = "okay";
			num-slots = <0x1>;
			cap-sd-highspeed;
			broken-cd;
			bus-width = <0x4>;
			altr,dw-mshc-ciu-div = <0x3>;
			altr,dw-mshc-sdr-timing = <0x0 0x3>;
		};

		nand@ffb90000 {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
			reg = <0xffb90000 0x72000 0xffb80000 0x10000>;
			reg-names = "nand_data", "denali_reg";
			interrupts = <0x0 0x63 0x4>;
			dma-mask = <0xffffffff>;
			clocks = <0x1f>;
			status = "disabled";
		};

		sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x40000>;
		};

		eccmgr@ffd06000 {
			compatible = "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <0x18>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			interrupts = <0x0 0x2 0x4 0x0 0x0 0x4>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ranges;

			sdramedac {
				compatible = "altr,sdram-edac-a10";
				altr,sdr-syscon = <0x20>;
				interrupts = <0x11 0x4 0x31 0x4>;
			};

			l2-ecc@ffd06010 {
				compatible = "altr,socfpga-a10-l2-ecc";
				reg = <0xffd06010 0x4>;
				interrupts = <0x0 0x4 0x20 0x4>;
			};

			ocram-ecc@ff8c3000 {
				compatible = "altr,socfpga-a10-ocram-ecc";
				reg = <0xff8c3000 0x400>;
				interrupts = <0x1 0x4 0x21 0x4>;
			};

			emac0-rx-ecc@ff8c0800 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0800 0x400>;
				altr,ecc-parent = <0x21>;
				interrupts = <0x4 0x4 0x24 0x4>;
			};

			emac0-tx-ecc@ff8c0c00 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0c00 0x400>;
				altr,ecc-parent = <0x21>;
				interrupts = <0x5 0x4 0x25 0x4>;
			};

			dma-ecc@ff8c8000 {
				compatible = "altr,socfpga-dma-ecc";
				reg = <0xff8c8000 0x400>;
				altr,ecc-parent = <0x1b>;
				interrupts = <0xa 0x4 0x2a 0x4>;
			};

			usb0-ecc@ff8c8800 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0xff8c8800 0x400>;
				altr,ecc-parent = <0x22>;
				interrupts = <0x2 0x4 0x22 0x4>;
			};
		};

		spi@ff809000 {
			compatible = "cdns,qspi-nor";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			reg = <0xff809000 0x100 0xffa00000 0x100000>;
			interrupts = <0x0 0x64 0x4>;
			cdns,fifo-depth = <0x80>;
			cdns,fifo-width = <0x4>;
			cdns,trigger-address = <0x0>;
			clocks = <0x23>;
			status = "disabled";
		};

		rstmgr@ffd05000 {
			#reset-cells = <0x1>;
			compatible = "altr,rst-mgr";
			reg = <0xffd05000 0x100>;
			altr,modrst-offset = <0x20>;
			linux,phandle = <0x19>;
			phandle = <0x19>;
		};

		snoop-control-unit@ffffc000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xffffc000 0x100>;
		};

		sysmgr@ffd06000 {
			compatible = "altr,sys-mgr", "syscon";
			reg = <0xffd06000 0x300>;
			cpu1-start-addr = <0xffd06230>;
			linux,phandle = <0x18>;
			phandle = <0x18>;
		};

		timer@ffffc600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xffffc600 0x100>;
			interrupts = <0x1 0xd 0xf04>;
			clocks = <0x24>;
		};

		timer0@ffc02700 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x0 0x73 0x4>;
			reg = <0xffc02700 0x100>;
			clocks = <0x1a>;
			clock-names = "timer";
		};

		timer1@ffc02800 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x0 0x74 0x4>;
			reg = <0xffc02800 0x100>;
			clocks = <0x1a>;
			clock-names = "timer";
		};

		timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x0 0x75 0x4>;
			reg = <0xffd00000 0x100>;
			clocks = <0x25>;
			clock-names = "timer";
		};

		timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x0 0x76 0x4>;
			reg = <0xffd01000 0x100>;
			clocks = <0x25>;
			clock-names = "timer";
		};

		serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0x0 0x6e 0x4>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		serial1@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0x0 0x6f 0x4>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			clocks = <0x1a>;
			status = "okay";
		};

		usbphy@0 {
			#phy-cells = <0x0>;
			compatible = "usb-nop-xceiv";
			status = "okay";
			linux,phandle = <0x27>;
			phandle = <0x27>;
		};

		usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0xffff>;
			interrupts = <0x0 0x5f 0x4>;
			clocks = <0x26>;
			clock-names = "otg";
			resets = <0x19 0x23>;
			reset-names = "dwc2";
			phys = <0x27>;
			phy-names = "usb2-phy";
			status = "okay";
			linux,phandle = <0x22>;
			phandle = <0x22>;
		};

		usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0xffff>;
			interrupts = <0x0 0x60 0x4>;
			clocks = <0x26>;
			clock-names = "otg";
			resets = <0x19 0x24>;
			reset-names = "dwc2";
			phys = <0x27>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0x0 0x77 0x4>;
			clocks = <0x25>;
			status = "okay";
		};

		watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0x0 0x78 0x4>;
			clocks = <0x25>;
			status = "disabled";
		};

		bridge@ff200000 {
			compatible = "simple-bus";
			reg = <0xff200000 0x200000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0xff200000 0x200000>;

			gpio@20 {
				compatible = "altr,pio-1.0";
				reg = <0x20 0x10>;
				altr,gpio-bank-width = <0x20>;
				resetvalue = <0x0>;
				#gpio-cells = <0x2>;
				gpio-controller;
				linux,phandle = <0x28>;
				phandle = <0x28>;
			};

			spi@40 {
				compatible = "altr,spi-1.0";
				reg = <0x40 0x20>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1a 0x4>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				ad9528-1@0 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#clock-cells = <0x1>;
					compatible = "ad9528";
					spi-max-frequency = <0x989680>;
					reg = <0x0>;
					clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
					adi,vcxo-freq = <0x7530000>;
					adi,refa-enable;
					adi,refa-diff-rcv-enable;
					adi,refa-r-div = <0x1>;
					adi,osc-in-cmos-neg-inp-enable;
					adi,pll1-feedback-div = <0x4>;
					adi,pll1-charge-pump-current-nA = <0x1388>;
					adi,pll2-vco-div-m1 = <0x3>;
					adi,pll2-n2-div = <0xa>;
					adi,pll2-r1-div = <0x1>;
					adi,pll2-charge-pump-current-nA = <0xc4888>;
					adi,sysref-src = <0x2>;
					adi,sysref-pattern-mode = <0x1>;
					adi,sysref-k-div = <0x200>;
					adi,sysref-request-enable;
					adi,sysref-nshot-mode = <0x3>;
					adi,sysref-request-trigger-mode = <0x0>;
					adi,rpole2 = <0x0>;
					adi,rzero = <0x7>;
					adi,cpole1 = <0x2>;
					adi,status-mon-pin0-function-select = <0x1>;
					adi,status-mon-pin1-function-select = <0x7>;
					reset-gpios = <0x28 0x1b 0x0>;
					linux,phandle = <0x2c>;
					phandle = <0x2c>;

					channel@13 {
						reg = <0xd>;
						adi,extended-name = "DEV_CLK";
						adi,driver-mode = <0x0>;
						adi,divider-phase = <0x0>;
						adi,channel-divider = <0xa>;
						adi,signal-source = <0x0>;
					};

					channel@1 {
						reg = <0x1>;
						adi,extended-name = "FMC_CLK";
						adi,driver-mode = <0x0>;
						adi,divider-phase = <0x0>;
						adi,channel-divider = <0xa>;
						adi,signal-source = <0x0>;
					};

					channel@12 {
						reg = <0xc>;
						adi,extended-name = "DEV_SYSREF";
						adi,driver-mode = <0x0>;
						adi,divider-phase = <0x0>;
						adi,channel-divider = <0xa>;
						adi,signal-source = <0x2>;
					};

					channel@3 {
						reg = <0x3>;
						adi,extended-name = "FMC_SYSREF";
						adi,driver-mode = <0x0>;
						adi,divider-phase = <0x0>;
						adi,channel-divider = <0xa>;
						adi,signal-source = <0x2>;
					};
				};

				ad9371-phy@1 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#clock-cells = <0x1>;
					compatible = "ad9371";
					reg = <0x1>;
					spi-max-frequency = <0x17d7840>;
					clocks = <0x29 0x2a 0x2b 0x2c 0xd 0x2c 0x1>;
					clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk";
					clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";
					adi,clocks-clk-pll-vco-freq_khz = <0x960000>;
					adi,clocks-device-clock_khz = <0x1e000>;
					adi,clocks-clk-pll-hs-div = <0x4>;
					adi,clocks-clk-pll-vco-div = <0x2>;
					adi,jesd204-obs-framer-over-sample = <0x0>;
					adi,rx-profile-adc-div = <0x1>;
					adi,rx-profile-en-high-rej-dec5 = <0x1>;
					adi,rx-profile-iq-rate_khz = <0x1e000>;
					adi,rx-profile-rf-bandwidth_hz = <0x5f5e100>;
					adi,rx-profile-rhb1-decimation = <0x1>;
					adi,rx-profile-rx-bbf-3db-corner_khz = <0x186a0>;
					adi,rx-profile-rx-dec5-decimation = <0x5>;
					adi,rx-profile-rx-fir-decimation = <0x2>;
					adi,obs-profile-adc-div = <0x1>;
					adi,obs-profile-en-high-rej-dec5 = <0x0>;
					adi,obs-profile-iq-rate_khz = <0x3c000>;
					adi,obs-profile-rf-bandwidth_hz = <0xbebc200>;
					adi,obs-profile-rhb1-decimation = <0x1>;
					adi,obs-profile-rx-bbf-3db-corner_khz = <0x186a0>;
					adi,obs-profile-rx-dec5-decimation = <0x5>;
					adi,obs-profile-rx-fir-decimation = <0x1>;
					adi,tx-profile-dac-div = <0x1>;
					adi,tx-profile-iq-rate_khz = <0x3c000>;
					adi,tx-profile-primary-sig-bandwidth_hz = <0x47868c0>;
					adi,tx-profile-rf-bandwidth_hz = <0xbebc200>;
					adi,tx-profile-thb1-interpolation = <0x2>;
					adi,tx-profile-thb2-interpolation = <0x1>;
					adi,tx-profile-tx-bbf-3db-corner_khz = <0x186a0>;
					adi,tx-profile-tx-dac-3db-corner_khz = <0x2e425>;
					adi,tx-profile-tx-fir-interpolation = <0x1>;
					adi,tx-profile-tx-input-hb-interpolation = <0x1>;
					adi,sniffer-profile-adc-div = <0x1>;
					adi,sniffer-profile-en-high-rej-dec5 = <0x0>;
					adi,sniffer-profile-iq-rate_khz = <0x7800>;
					adi,sniffer-profile-rf-bandwidth_hz = <0x1312d00>;
					adi,sniffer-profile-rhb1-decimation = <0x2>;
					adi,sniffer-profile-rx-bbf-3db-corner_khz = <0x186a0>;
					adi,sniffer-profile-rx-dec5-decimation = <0x5>;
					adi,sniffer-profile-rx-fir-decimation = <0x4>;
					reset-gpios = <0x28 0x14 0x0>;
					test-gpios = <0x28 0x15 0x0>;
					sysref_req-gpios = <0x28 0x1a 0x0>;
					rx2_enable-gpios = <0x28 0x16 0x0>;
					rx1_enable-gpios = <0x28 0x17 0x0>;
					tx2_enable-gpios = <0x28 0x18 0x0>;
					tx1_enable-gpios = <0x28 0x19 0x0>;
					linux,phandle = <0x36>;
					phandle = <0x36>;
				};
			};

			axi-jesd204-tx@20000 {
				compatible = "adi,axi-jesd204-tx-1.0";
				reg = <0x20000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1c 0x0>;
				clocks = <0x2d 0x2e 0x2f>;
				clock-names = "s_axi_aclk", "device_clk", "lane_clk";
				adi,octets-per-frame = <0x2>;
				adi,frames-per-multiframe = <0x20>;
				adi,converter-resolution = <0xe>;
				adi,bits-per-sample = <0x10>;
				adi,converters-per-device = <0x4>;
				adi,control-bits-per-sample = <0x2>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd_tx_lane_clk";
				linux,phandle = <0x2a>;
				phandle = <0x2a>;
			};

			axi-jesd204-rx@30000 {
				compatible = "adi,axi-jesd204-rx-1.0";
				reg = <0x30000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1b 0x0>;
				clocks = <0x2d 0x30 0x31>;
				clock-names = "s_axi_aclk", "device_clk", "lane_clk";
				adi,octets-per-frame = <0x4>;
				adi,frames-per-multiframe = <0x20>;
				adi,converter-resolution = <0x10>;
				adi,bits-per-sample = <0x10>;
				adi,converters-per-device = <0x4>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd_rx_lane_clk";
				linux,phandle = <0x29>;
				phandle = <0x29>;
			};

			axi-jesd204-rx@40000 {
				compatible = "adi,axi-jesd204-rx-1.0";
				reg = <0x40000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1d 0x0>;
				clocks = <0x2d 0x32 0x33>;
				clock-names = "s_axi_aclk", "device_clk", "lane_clk";
				adi,octets-per-frame = <0x2>;
				adi,frames-per-multiframe = <0x20>;
				adi,converter-resolution = <0x10>;
				adi,bits-per-sample = <0x10>;
				adi,converters-per-device = <0x4>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd_rx_os_lane_clk";
				linux,phandle = <0x2b>;
				phandle = <0x2b>;
			};

			axi-ad9371-tx-xcvr@24000 {
				compatible = "adi,altera-adxcvr-1.00.a";
				reg = <0x24000 0x1000 0x26000 0x1000 0x28000 0x1000 0x29000 0x1000 0x2a000 0x1000 0x2b000 0x1000>;
				reg-names = "adxcvr", "atx-pll", "adxcfg-0", "adxcfg-1", "adxcfg-2", "adxcfg-3";
				clocks = <0x2c 0x1 0x2e>;
				clock-names = "ref", "link";
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_tx_lane_clock";
				linux,phandle = <0x2f>;
				phandle = <0x2f>;
			};

			axi-ad9371-rx-xcvr@34000 {
				compatible = "adi,altera-adxcvr-1.00.a";
				reg = <0x34000 0x1000 0x38000 0x1000 0x39000 0x1000>;
				reg-names = "adxcvr", "adxcfg-0", "adxcfg-1";
				clocks = <0x2c 0x1 0x30>;
				clock-names = "ref", "link";
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_rx_lane_clock";
				linux,phandle = <0x31>;
				phandle = <0x31>;
			};

			axi-ad9371-rx-os-xcvr@44000 {
				compatible = "adi,altera-adxcvr-1.00.a";
				reg = <0x44000 0x1000 0x48000 0x1000 0x49000 0x1000>;
				reg-names = "adxcvr", "adxcfg-0", "adxcfg-1";
				clocks = <0x2c 0x1 0x32>;
				clock-names = "ref", "link";
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_rx_os_lane_clock";
				linux,phandle = <0x33>;
				phandle = <0x33>;
			};

			axi-ad9371-tx-dma@2c000 {
				compatible = "adi,axi-dmac-1.00.a";
				reg = <0x2c000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1e 0x4>;
				#dma-cells = <0x1>;
				clocks = <0x34>;
				linux,phandle = <0x37>;
				phandle = <0x37>;

				dma-channel {
					adi,source-bus-width = <0x80>;
					adi,destination-bus-width = <0x80>;
					adi,type = <0x1>;
				};
			};

			axi-ad9371-rx-dma@3c000 {
				compatible = "adi,axi-dmac-1.00.a";
				reg = <0x3c000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1f 0x4>;
				#dma-cells = <0x1>;
				clocks = <0x34>;
				linux,phandle = <0x35>;
				phandle = <0x35>;

				dma-channel {
					adi,source-bus-width = <0x40>;
					adi,destination-bus-width = <0x80>;
					adi,type = <0x0>;
				};
			};

			axi-ad9371-rx-os-dma@4c000 {
				compatible = "adi,axi-dmac-1.00.a";
				reg = <0x4c000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x20 0x4>;
				#dma-cells = <0x1>;
				clocks = <0x34>;
				linux,phandle = <0x38>;
				phandle = <0x38>;

				dma-channel {
					adi,source-bus-width = <0x40>;
					adi,destination-bus-width = <0x80>;
					adi,type = <0x0>;
				};
			};

			axi-ad9371-rx-hpc@50000 {
				compatible = "adi,axi-ad9371-rx-1.0";
				reg = <0x50000 0x8000>;
				dmas = <0x35 0x0>;
				dma-names = "rx";
				spibus-connected = <0x36>;
			};

			axi-ad9371-tx-hpc@54000 {
				compatible = "adi,axi-ad9371-tx-1.0";
				reg = <0x54000 0x4000>;
				dmas = <0x37 0x0>;
				dma-names = "tx";
				clocks = <0x36 0x2>;
				clock-names = "sampl_clk";
				spibus-connected = <0x36>;
				adi,axi-pl-fifo-enable;
				plddrbypass-gpios = <0x28 0x1c 0x0>;
			};

			axi-ad9371-rx-obs-hpc@58000 {
				compatible = "adi,axi-ad9371-obs-1.0";
				reg = <0x58000 0x1000>;
				dmas = <0x38 0x0>;
				dma-names = "rx";
				clocks = <0x36 0x1>;
				clock-names = "sampl_clk";
			};

			altera-a10-fpll@25000 {
				compatible = "altr,a10-fpll";
				reg = <0x25000 0x1000>;
				clocks = <0x2c 0x1>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_tx_link_clock";
				linux,phandle = <0x2e>;
				phandle = <0x2e>;
			};

			altera-a10-fpll@35000 {
				compatible = "altr,a10-fpll";
				reg = <0x35000 0x1000>;
				clocks = <0x2c 0x1>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_rx_link_clock";
				linux,phandle = <0x30>;
				phandle = <0x30>;
			};

			altera-a10-fpll@45000 {
				compatible = "altr,a10-fpll";
				reg = <0x45000 0x1000>;
				clocks = <0x2c 0x1>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_rx_os_link_clock";
				linux,phandle = <0x32>;
				phandle = <0x32>;
			};
		};
	};

	a10leds {
		compatible = "gpio-leds";

		a10sr_led0 {
			label = "a10sr-led0";
			gpios = <0x39 0x0 0x1>;
		};

		a10sr_led1 {
			label = "a10sr-led1";
			gpios = <0x39 0x1 0x1>;
		};

		a10sr_led2 {
			label = "a10sr-led2";
			gpios = <0x39 0x2 0x1>;
		};

		a10sr_led3 {
			label = "a10sr-led3";
			gpios = <0x39 0x3 0x1>;
		};
	};

	clocks {

		sys_clk {
			#clock-cells = <0x0>;
			compatible = "fixed-clock";
			clock-frequency = <0x5f5e100>;
			clock-output-names = "system_clock";
			linux,phandle = <0x2d>;
			phandle = <0x2d>;
		};

		dma_clk {
			#clock-cells = <0x0>;
			compatible = "fixed-clock";
			clock-frequency = <0xee6b280>;
			clock-output-names = "dma_clk";
			linux,phandle = <0x34>;
			phandle = <0x34>;
		};

		clock@0 {
			#clock-cells = <0x0>;
			compatible = "fixed-clock";
			clock-frequency = <0xbb8000>;
			clock-output-names = "ad9371_ext_refclk";
		};
	};
};

For testing with different frame sizes, here are my findings:

With a Tx cyclic frame size of 3072

Rx Frame Size
4000 - no corrupt frame
4100 - no corrupt frame
3072*2 - corrupt frame observed 
8000 - corrupt frame observed

With a Tx cyclic frame size of 6144

Rx frame tested
4000 - no corrupt frame
4100 - no corrupt frame
6144 - corrupt frame observed 
8000 - corrupt frame observed

As suspected, the problem is most likely is independent of the transmitter frame size

Reply

0 dglee

on Nov 9, 2018 12:20 PM in reply to ADIApproved

[    1.232224] altera-a10-fpll ff245000.altera-a10-fpll: FPLL PLL calibration OK (1400 us)
[    1.234131] altera-a10-fpll ff235000.altera-a10-fpll: FPLL PLL calibration OK (1400 us)
[    1.236153] altera-a10-fpll ff225000.altera-a10-fpll: FPLL PLL calibration OK (1400 us)
[    1.275209] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: ATX PLL calibration OK (20 ms)
[    1.298438] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Lane 0 TX termination and VOD calibration OK (600 us)
[    1.333594] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Lane 1 TX termination and VOD calibration OK (600 us)
[    1.349425] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Lane 2 TX termination and VOD calibration OK (600 us)
[    1.378946] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Lane 3 TX termination and VOD calibration OK (600 us)
[    1.388769] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Altera ADXCVR (16.01.a) probed
[    1.401306] altera_adxcvr ff234000.axi-ad9371-rx-xcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
[    1.415333] altera_adxcvr ff234000.axi-ad9371-rx-xcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
[    1.425228] altera_adxcvr ff234000.axi-ad9371-rx-xcvr: Altera ADXCVR (16.01.a) probed
[    1.437920] altera_adxcvr ff244000.axi-ad9371-rx-os-xcvr: Lane 0 CDR/CMU PLL & RX offset calibration OK (600 us)
[    1.451858] altera_adxcvr ff244000.axi-ad9371-rx-os-xcvr: Lane 1 CDR/CMU PLL & RX offset calibration OK (600 us)
[    1.462006] altera_adxcvr ff244000.axi-ad9371-rx-os-xcvr: Altera ADXCVR (16.01.a) probed
[    1.470487] fpga_manager fpga0: SoCFPGA Arria10 FPGA Manager registered
[    1.477537] oprofile: no performance counters
[    1.481984] oprofile: using timer interrupt.
[    1.486885] NET: Registered protocol family 10
[    1.491652] altera_adxcvr ff224000.axi-ad9371-tx-xcvr: Setting link rate to 122880000 (lane rate: 4915200)
[    1.501767] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    1.502327] altera_adxcvr ff234000.axi-ad9371-rx-xcvr: Setting link rate to 122880000 (lane rate: 4915200)
[    1.503341] altera_adxcvr ff244000.axi-ad9371-rx-os-xcvr: Setting link rate to 122880000 (lane rate: 4915200)
[    1.527719] NET: Registered protocol family 17
[    1.532179] NET: Registered protocol family 15
[    1.536603] can: controller area network core (rev 20120528 abi 9)
[    1.542807] NET: Registered protocol family 29
[    1.547231] can: raw protocol (rev 20120528)
[    1.551479] can: broadcast manager protocol (rev 20161123 t)
[    1.557120] can: netlink gateway (rev 20130117) max_hops=1
[    1.562764] 8021q: 802.1Q VLAN Support v1.8
[    1.566962] Key type dns_resolver registered
[    1.571266] ThumbEE CPU extension supported.
[    1.575534] Registering SWP/SWPB emulation handler
[    1.582822] ad9371 spi32766.1: ad9371_probe : enter
[    1.589113] ad9371 spi32766.1: ad9371_probe : enter
[    3.280171] random: crng init done
[   29.086754] ad9371 spi32766.1: framerStatus (0x20)
[   29.154287] ad9371 spi32766.1: ad9371_probe : AD9371 Rev 4, Firmware 5.1.1 API version: 1.5.1.3565 successfully initialized
[   29.176743] cf_axi_dds ff254000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0xFF254000 mapped to 0xf09a0000, probed DDS AD9371
[   29.210875] cf_axi_adc ff250000.axi-ad9371-rx-hpc: ADI AIM (10.00.b) at 0xFF250000 mapped to 0xf09a8000, probed ADC AD9371 as MASTER

Device tree

/dts-v1/;

/ {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	model = "Altera SOCFPGA Arria 10";
	compatible = "altr,socfpga-arria10", "altr,socfpga";

	chosen {
		bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p3 rw rootwait earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	aliases {
		ethernet0 = "/soc/ethernet@ff800000";
		serial0 = "/soc/serial1@ffc02100";
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		enable-method = "altr,socfpga-a10-smp";

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x0>;
			next-level-cache = <0x1>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x1>;
			next-level-cache = <0x1>;
		};
	};

	intc@ffffd000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <0x3>;
		interrupt-controller;
		reg = <0xffffd000 0x1000 0xffffc100 0x100>;
		linux,phandle = <0x2>;
		phandle = <0x2>;
	};

	soc {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <0x2>;
		ranges;

		amba {
			compatible = "simple-bus";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;

			pdma@ffda1000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0xffda1000 0x1000>;
				interrupts = <0x0 0x53 0x4 0x0 0x54 0x4 0x0 0x55 0x4 0x0 0x56 0x4 0x0 0x57 0x4 0x0 0x58 0x4 0x0 0x59 0x4 0x0 0x5a 0x4 0x0 0x5b 0x4>;
				#dma-cells = <0x1>;
				#dma-channels = <0x8>;
				#dma-requests = <0x20>;
				clocks = <0x3>;
				clock-names = "apb_pclk";
				microcode-cached;
				linux,phandle = <0x1b>;
				phandle = <0x1b>;
			};
		};

		base_fpga_region {
			#address-cells = <0x2>;
			#size-cells = <0x1>;
			compatible = "fpga-region", "simple-bus";
			fpga-mgr = <0x4>;
			ranges = <0x0 0x0 0xc0000000 0x20000000 0x1 0x0 0xff200000 0x200000>;

			bridge0@0x0 {
				compatible = "simple-bus";
				#size-cells = <0x1>;
				#address-cells = <0x1>;
				ranges = <0x0 0x0 0x0 0x20000000>;

				mwipcore@0x00000000 {
					status = "disabled";
					compatible = "mathworks,mwipcore-v3.00";
					reg = <0x0 0x10000>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					mmrd-channel@0 {
						status = "disabled";
						reg = <0x0>;
						compatible = "mathworks,mm-read-channel-v1.00";
						mathworks,dev-name = "mmrd0";
					};

					mmwr-channel@1 {
						status = "disabled";
						reg = <0x1>;
						compatible = "mathworks,mm-write-channel-v1.00";
						mathworks,dev-name = "mmwr0";
					};
				};
			};

			bridge1@0x1 {
				compatible = "simple-bus";
				#size-cells = <0x1>;
				#address-cells = <0x1>;
				ranges = <0x0 0x1 0x0 0x200000>;
			};
		};

		clkmgr@ffd04000 {
			compatible = "altr,clk-mgr";
			reg = <0xffd04000 0x1000>;

			clocks {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				cb_intosc_hs_div2_clk {
					#clock-cells = <0x0>;
					compatible = "fixed-clock";
					linux,phandle = <0xd>;
					phandle = <0xd>;
				};

				cb_intosc_ls_clk {
					#clock-cells = <0x0>;
					compatible = "fixed-clock";
					linux,phandle = <0x6>;
					phandle = <0x6>;
				};

				f2s_free_clk {
					#clock-cells = <0x0>;
					compatible = "fixed-clock";
					linux,phandle = <0x7>;
					phandle = <0x7>;
				};

				osc1 {
					#clock-cells = <0x0>;
					compatible = "fixed-clock";
					clock-frequency = <0x17d7840>;
					linux,phandle = <0x5>;
					phandle = <0x5>;
				};

				main_pll {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-pll-clock";
					clocks = <0x5 0x6 0x7>;
					reg = <0x40>;
					linux,phandle = <0x8>;
					phandle = <0x8>;

					main_mpu_base_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						div-reg = <0x140 0x0 0xb>;
						linux,phandle = <0xb>;
						phandle = <0xb>;
					};

					main_noc_base_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						div-reg = <0x144 0x0 0xb>;
						linux,phandle = <0xe>;
						phandle = <0xe>;
					};

					main_emaca_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x68>;
					};

					main_emacb_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x6c>;
					};

					main_emac_ptp_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x70>;
					};

					main_gpio_db_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x74>;
					};

					main_sdmmc_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x78>;
						linux,phandle = <0x12>;
						phandle = <0x12>;
					};

					main_s2f_usr0_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x7c>;
					};

					main_s2f_usr1_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x80>;
						linux,phandle = <0x10>;
						phandle = <0x10>;
					};

					main_hmc_pll_ref_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x84>;
					};

					main_periph_ref_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x8>;
						reg = <0x9c>;
						linux,phandle = <0x9>;
						phandle = <0x9>;
					};
				};

				periph_pll {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-pll-clock";
					clocks = <0x5 0x6 0x7 0x9>;
					reg = <0xc0>;
					linux,phandle = <0xa>;
					phandle = <0xa>;

					peri_mpu_base_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						div-reg = <0x140 0x10 0xb>;
						linux,phandle = <0xc>;
						phandle = <0xc>;
					};

					peri_noc_base_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						div-reg = <0x144 0x10 0xb>;
						linux,phandle = <0xf>;
						phandle = <0xf>;
					};

					peri_emaca_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xe8>;
					};

					peri_emacb_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xec>;
					};

					peri_emac_ptp_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xf0>;
					};

					peri_gpio_db_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xf4>;
					};

					peri_sdmmc_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xf8>;
						linux,phandle = <0x13>;
						phandle = <0x13>;
					};

					peri_s2f_usr0_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0xfc>;
					};

					peri_s2f_usr1_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0x100>;
						linux,phandle = <0x11>;
						phandle = <0x11>;
					};

					peri_hmc_pll_ref_clk {
						#clock-cells = <0x0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0xa>;
						reg = <0x104>;
					};
				};

				mpu_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0xb 0xc 0x5 0xd 0x7>;
					reg = <0x60>;
					linux,phandle = <0x15>;
					phandle = <0x15>;
				};

				noc_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0xe 0xf 0x5 0xd 0x7>;
					reg = <0x64>;
					linux,phandle = <0x14>;
					phandle = <0x14>;
				};

				s2f_user1_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x10 0x11 0x5 0xd 0x7>;
					reg = <0x104>;
				};

				sdmmc_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x12 0x13 0x5 0xd 0x7>;
					fixed-divider = <0x4>;
					reg = <0xf8>;
					linux,phandle = <0x16>;
					phandle = <0x16>;
				};

				l4_sys_free_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x14>;
					fixed-divider = <0x4>;
					linux,phandle = <0x25>;
					phandle = <0x25>;
				};

				l4_main_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x14>;
					div-reg = <0xa8 0x0 0x2>;
					clk-gate = <0x48 0x1>;
					linux,phandle = <0x3>;
					phandle = <0x3>;
				};

				l4_mp_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x14>;
					div-reg = <0xa8 0x8 0x2>;
					clk-gate = <0x48 0x2>;
					linux,phandle = <0x17>;
					phandle = <0x17>;
				};

				l4_sp_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x14>;
					div-reg = <0xa8 0x10 0x2>;
					clk-gate = <0x48 0x3>;
					linux,phandle = <0x1a>;
					phandle = <0x1a>;
				};

				mpu_periph_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x15>;
					fixed-divider = <0x4>;
					clk-gate = <0x48 0x0>;
					linux,phandle = <0x24>;
					phandle = <0x24>;
				};

				sdmmc_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x16>;
					clk-gate = <0xc8 0x5>;
					clk-phase = <0x0 0x87>;
					linux,phandle = <0x1e>;
					phandle = <0x1e>;
				};

				qspi_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x3>;
					clk-gate = <0xc8 0xb>;
					linux,phandle = <0x23>;
					phandle = <0x23>;
				};

				nand_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x17>;
					clk-gate = <0xc8 0xa>;
					linux,phandle = <0x1f>;
					phandle = <0x1f>;
				};

				spi_m_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x3>;
					clk-gate = <0xc8 0x9>;
					linux,phandle = <0x1c>;
					phandle = <0x1c>;
				};

				usb_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x17>;
					clk-gate = <0xc8 0x8>;
					linux,phandle = <0x26>;
					phandle = <0x26>;
				};

				s2f_usr1_clk {
					#clock-cells = <0x0>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x11>;
					clk-gate = <0xc8 0x6>;
				};
			};
		};

		ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <0x18 0x44 0x0>;
			reg = <0xff800000 0x2000>;
			interrupts = <0x0 0x5c 0x4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <0x100>;
			snps,perfect-filter-entries = <0x80>;
			tx-fifo-depth = <0x1000>;
			rx-fifo-depth = <0x4000>;
			clocks = <0x17>;
			clock-names = "stmmaceth";
			resets = <0x19 0x20>;
			reset-names = "stmmaceth";
			status = "okay";
			phy-mode = "rgmii";
			phy-addr = <0xffffffff>;
			txd0-skew-ps = <0x0>;
			txd1-skew-ps = <0x0>;
			txd2-skew-ps = <0x0>;
			txd3-skew-ps = <0x0>;
			rxd0-skew-ps = <0x1a4>;
			rxd1-skew-ps = <0x1a4>;
			rxd2-skew-ps = <0x1a4>;
			rxd3-skew-ps = <0x1a4>;
			txen-skew-ps = <0x0>;
			txc-skew-ps = <0x744>;
			rxdv-skew-ps = <0x1a4>;
			rxc-skew-ps = <0x690>;
			max-frame-size = <0xed8>;
			linux,phandle = <0x21>;
			phandle = <0x21>;
		};

		ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <0x18 0x48 0x0>;
			reg = <0xff802000 0x2000>;
			interrupts = <0x0 0x5d 0x4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <0x100>;
			snps,perfect-filter-entries = <0x80>;
			tx-fifo-depth = <0x1000>;
			rx-fifo-depth = <0x4000>;
			clocks = <0x17>;
			clock-names = "stmmaceth";
			resets = <0x19 0x21>;
			reset-names = "stmmaceth";
			status = "disabled";
		};

		ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <0x18 0x4c 0x0>;
			reg = <0xff804000 0x2000>;
			interrupts = <0x0 0x5e 0x4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <0x100>;
			snps,perfect-filter-entries = <0x80>;
			tx-fifo-depth = <0x1000>;
			rx-fifo-depth = <0x4000>;
			clocks = <0x17>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gpio@ffc02900 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02900 0x100>;
			status = "disabled";

			gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <0x2>;
				snps,nr-gpios = <0x1d>;
				reg = <0x0>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupts = <0x0 0x70 0x4>;
			};
		};

		gpio@ffc02a00 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02a00 0x100>;
			status = "okay";

			gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <0x2>;
				snps,nr-gpios = <0x1d>;
				reg = <0x0>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupts = <0x0 0x71 0x4>;
				linux,phandle = <0x1d>;
				phandle = <0x1d>;
			};
		};

		gpio@ffc02b00 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02b00 0x100>;
			status = "disabled";

			gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <0x2>;
				snps,nr-gpios = <0x1b>;
				reg = <0x0>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupts = <0x0 0x72 0x4>;
			};
		};

		fpga-mgr@ffd03000 {
			compatible = "altr,socfpga-a10-fpga-mgr";
			reg = <0xffd03000 0x100 0xffcfe400 0x20>;
			clocks = <0x17>;
			resets = <0x19 0x83>;
			reset-names = "fpgamgr";
			linux,phandle = <0x4>;
			phandle = <0x4>;
		};

		i2c@ffc02200 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02200 0x100>;
			interrupts = <0x0 0x69 0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		i2c@ffc02300 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02300 0x100>;
			interrupts = <0x0 0x6a 0x4>;
			clocks = <0x1a>;
			status = "okay";
			clock-frequency = <0x186a0>;
			i2c-sda-falling-time-ns = <0x1770>;
			i2c-scl-falling-time-ns = <0x1770>;

			lcd@28 {
				compatible = "newhaven,nhd-0216k3z-nsw-bbw";
				reg = <0x28>;
				height = <0x2>;
				width = <0x10>;
				brightness = <0x8>;
			};

			eeprom@51 {
				compatible = "atmel,24c32";
				reg = <0x51>;
				pagesize = <0x20>;
			};

			rtc@68 {
				compatible = "dallas,ds1339";
				reg = <0x68>;
			};

			max@4c {
				compatible = "max1619";
				reg = <0x4c>;
			};

			ltc@5c {
				compatible = "ltc2977";
				reg = <0x5c>;
			};
		};

		i2c@ffc02400 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02400 0x100>;
			interrupts = <0x0 0x6b 0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		i2c@ffc02500 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02500 0x100>;
			interrupts = <0x0 0x6c 0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		i2c@ffc02600 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02600 0x100>;
			interrupts = <0x0 0x6d 0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		spi@ffda5000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			reg = <0xffda5000 0x100>;
			interrupts = <0x0 0x66 0x4>;
			num-chipselect = <0x4>;
			bus-num = <0x0>;
			tx-dma-channel = <0x1b 0x10>;
			rx-dma-channel = <0x1b 0x11>;
			clocks = <0x1c>;
			status = "okay";

			resource-manager@0 {
				compatible = "altr,a10sr";
				reg = <0x0>;
				spi-max-frequency = <0x186a0>;
				interrupt-parent = <0x1d>;
				interrupts = <0x5 0x8>;
				interrupt-controller;
				#interrupt-cells = <0x2>;

				gpio-controller {
					compatible = "altr,a10sr-gpio";
					gpio-controller;
					#gpio-cells = <0x2>;
					linux,phandle = <0x39>;
					phandle = <0x39>;
				};

				ps_alarm {
					compatible = "altr,a10sr-hwmon";
				};
			};
		};

		sdr@ffc25000 {
			compatible = "altr,sdr-ctl", "syscon";
			reg = <0xffcfb100 0x80>;
			linux,phandle = <0x20>;
			phandle = <0x20>;
		};

		l2-cache@fffff000 {
			compatible = "arm,pl310-cache";
			reg = <0xfffff000 0x1000>;
			interrupts = <0x0 0x12 0x4>;
			cache-unified;
			cache-level = <0x2>;
			prefetch-data = <0x1>;
			prefetch-instr = <0x1>;
			arm,shared-override;
			linux,phandle = <0x1>;
			phandle = <0x1>;
		};

		dwmmc0@ff808000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0x0 0x62 0x4>;
			fifo-depth = <0x400>;
			clocks = <0x17 0x1e>;
			clock-names = "biu", "ciu";
			status = "okay";
			num-slots = <0x1>;
			cap-sd-highspeed;
			broken-cd;
			bus-width = <0x4>;
			altr,dw-mshc-ciu-div = <0x3>;
			altr,dw-mshc-sdr-timing = <0x0 0x3>;
		};

		nand@ffb90000 {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
			reg = <0xffb90000 0x72000 0xffb80000 0x10000>;
			reg-names = "nand_data", "denali_reg";
			interrupts = <0x0 0x63 0x4>;
			dma-mask = <0xffffffff>;
			clocks = <0x1f>;
			status = "disabled";
		};

		sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x40000>;
		};

		eccmgr@ffd06000 {
			compatible = "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <0x18>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			interrupts = <0x0 0x2 0x4 0x0 0x0 0x4>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ranges;

			sdramedac {
				compatible = "altr,sdram-edac-a10";
				altr,sdr-syscon = <0x20>;
				interrupts = <0x11 0x4 0x31 0x4>;
			};

			l2-ecc@ffd06010 {
				compatible = "altr,socfpga-a10-l2-ecc";
				reg = <0xffd06010 0x4>;
				interrupts = <0x0 0x4 0x20 0x4>;
			};

			ocram-ecc@ff8c3000 {
				compatible = "altr,socfpga-a10-ocram-ecc";
				reg = <0xff8c3000 0x400>;
				interrupts = <0x1 0x4 0x21 0x4>;
			};

			emac0-rx-ecc@ff8c0800 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0800 0x400>;
				altr,ecc-parent = <0x21>;
				interrupts = <0x4 0x4 0x24 0x4>;
			};

			emac0-tx-ecc@ff8c0c00 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0c00 0x400>;
				altr,ecc-parent = <0x21>;
				interrupts = <0x5 0x4 0x25 0x4>;
			};

			dma-ecc@ff8c8000 {
				compatible = "altr,socfpga-dma-ecc";
				reg = <0xff8c8000 0x400>;
				altr,ecc-parent = <0x1b>;
				interrupts = <0xa 0x4 0x2a 0x4>;
			};

			usb0-ecc@ff8c8800 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0xff8c8800 0x400>;
				altr,ecc-parent = <0x22>;
				interrupts = <0x2 0x4 0x22 0x4>;
			};
		};

		spi@ff809000 {
			compatible = "cdns,qspi-nor";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			reg = <0xff809000 0x100 0xffa00000 0x100000>;
			interrupts = <0x0 0x64 0x4>;
			cdns,fifo-depth = <0x80>;
			cdns,fifo-width = <0x4>;
			cdns,trigger-address = <0x0>;
			clocks = <0x23>;
			status = "disabled";
		};

		rstmgr@ffd05000 {
			#reset-cells = <0x1>;
			compatible = "altr,rst-mgr";
			reg = <0xffd05000 0x100>;
			altr,modrst-offset = <0x20>;
			linux,phandle = <0x19>;
			phandle = <0x19>;
		};

		snoop-control-unit@ffffc000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xffffc000 0x100>;
		};

		sysmgr@ffd06000 {
			compatible = "altr,sys-mgr", "syscon";
			reg = <0xffd06000 0x300>;
			cpu1-start-addr = <0xffd06230>;
			linux,phandle = <0x18>;
			phandle = <0x18>;
		};

		timer@ffffc600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xffffc600 0x100>;
			interrupts = <0x1 0xd 0xf04>;
			clocks = <0x24>;
		};

		timer0@ffc02700 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x0 0x73 0x4>;
			reg = <0xffc02700 0x100>;
			clocks = <0x1a>;
			clock-names = "timer";
		};

		timer1@ffc02800 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x0 0x74 0x4>;
			reg = <0xffc02800 0x100>;
			clocks = <0x1a>;
			clock-names = "timer";
		};

		timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x0 0x75 0x4>;
			reg = <0xffd00000 0x100>;
			clocks = <0x25>;
			clock-names = "timer";
		};

		timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x0 0x76 0x4>;
			reg = <0xffd01000 0x100>;
			clocks = <0x25>;
			clock-names = "timer";
		};

		serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0x0 0x6e 0x4>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			clocks = <0x1a>;
			status = "disabled";
		};

		serial1@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0x0 0x6f 0x4>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			clocks = <0x1a>;
			status = "okay";
		};

		usbphy@0 {
			#phy-cells = <0x0>;
			compatible = "usb-nop-xceiv";
			status = "okay";
			linux,phandle = <0x27>;
			phandle = <0x27>;
		};

		usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0xffff>;
			interrupts = <0x0 0x5f 0x4>;
			clocks = <0x26>;
			clock-names = "otg";
			resets = <0x19 0x23>;
			reset-names = "dwc2";
			phys = <0x27>;
			phy-names = "usb2-phy";
			status = "okay";
			linux,phandle = <0x22>;
			phandle = <0x22>;
		};

		usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0xffff>;
			interrupts = <0x0 0x60 0x4>;
			clocks = <0x26>;
			clock-names = "otg";
			resets = <0x19 0x24>;
			reset-names = "dwc2";
			phys = <0x27>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0x0 0x77 0x4>;
			clocks = <0x25>;
			status = "okay";
		};

		watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0x0 0x78 0x4>;
			clocks = <0x25>;
			status = "disabled";
		};

		bridge@ff200000 {
			compatible = "simple-bus";
			reg = <0xff200000 0x200000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0xff200000 0x200000>;

			gpio@20 {
				compatible = "altr,pio-1.0";
				reg = <0x20 0x10>;
				altr,gpio-bank-width = <0x20>;
				resetvalue = <0x0>;
				#gpio-cells = <0x2>;
				gpio-controller;
				linux,phandle = <0x28>;
				phandle = <0x28>;
			};

			spi@40 {
				compatible = "altr,spi-1.0";
				reg = <0x40 0x20>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1a 0x4>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				ad9528-1@0 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#clock-cells = <0x1>;
					compatible = "ad9528";
					spi-max-frequency = <0x989680>;
					reg = <0x0>;
					clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
					adi,vcxo-freq = <0x7530000>;
					adi,refa-enable;
					adi,refa-diff-rcv-enable;
					adi,refa-r-div = <0x1>;
					adi,osc-in-cmos-neg-inp-enable;
					adi,pll1-feedback-div = <0x4>;
					adi,pll1-charge-pump-current-nA = <0x1388>;
					adi,pll2-vco-div-m1 = <0x3>;
					adi,pll2-n2-div = <0xa>;
					adi,pll2-r1-div = <0x1>;
					adi,pll2-charge-pump-current-nA = <0xc4888>;
					adi,sysref-src = <0x2>;
					adi,sysref-pattern-mode = <0x1>;
					adi,sysref-k-div = <0x200>;
					adi,sysref-request-enable;
					adi,sysref-nshot-mode = <0x3>;
					adi,sysref-request-trigger-mode = <0x0>;
					adi,rpole2 = <0x0>;
					adi,rzero = <0x7>;
					adi,cpole1 = <0x2>;
					adi,status-mon-pin0-function-select = <0x1>;
					adi,status-mon-pin1-function-select = <0x7>;
					reset-gpios = <0x28 0x1b 0x0>;
					linux,phandle = <0x2c>;
					phandle = <0x2c>;

					channel@13 {
						reg = <0xd>;
						adi,extended-name = "DEV_CLK";
						adi,driver-mode = <0x0>;
						adi,divider-phase = <0x0>;
						adi,channel-divider = <0xa>;
						adi,signal-source = <0x0>;
					};

					channel@1 {
						reg = <0x1>;
						adi,extended-name = "FMC_CLK";
						adi,driver-mode = <0x0>;
						adi,divider-phase = <0x0>;
						adi,channel-divider = <0xa>;
						adi,signal-source = <0x0>;
					};

					channel@12 {
						reg = <0xc>;
						adi,extended-name = "DEV_SYSREF";
						adi,driver-mode = <0x0>;
						adi,divider-phase = <0x0>;
						adi,channel-divider = <0xa>;
						adi,signal-source = <0x2>;
					};

					channel@3 {
						reg = <0x3>;
						adi,extended-name = "FMC_SYSREF";
						adi,driver-mode = <0x0>;
						adi,divider-phase = <0x0>;
						adi,channel-divider = <0xa>;
						adi,signal-source = <0x2>;
					};
				};

				ad9371-phy@1 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#clock-cells = <0x1>;
					compatible = "ad9371";
					reg = <0x1>;
					spi-max-frequency = <0x17d7840>;
					clocks = <0x29 0x2a 0x2b 0x2c 0xd 0x2c 0x1>;
					clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk";
					clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";
					adi,clocks-clk-pll-vco-freq_khz = <0x960000>;
					adi,clocks-device-clock_khz = <0x1e000>;
					adi,clocks-clk-pll-hs-div = <0x4>;
					adi,clocks-clk-pll-vco-div = <0x2>;
					adi,jesd204-obs-framer-over-sample = <0x0>;
					adi,rx-profile-adc-div = <0x1>;
					adi,rx-profile-en-high-rej-dec5 = <0x1>;
					adi,rx-profile-iq-rate_khz = <0x1e000>;
					adi,rx-profile-rf-bandwidth_hz = <0x5f5e100>;
					adi,rx-profile-rhb1-decimation = <0x1>;
					adi,rx-profile-rx-bbf-3db-corner_khz = <0x186a0>;
					adi,rx-profile-rx-dec5-decimation = <0x5>;
					adi,rx-profile-rx-fir-decimation = <0x2>;
					adi,obs-profile-adc-div = <0x1>;
					adi,obs-profile-en-high-rej-dec5 = <0x0>;
					adi,obs-profile-iq-rate_khz = <0x3c000>;
					adi,obs-profile-rf-bandwidth_hz = <0xbebc200>;
					adi,obs-profile-rhb1-decimation = <0x1>;
					adi,obs-profile-rx-bbf-3db-corner_khz = <0x186a0>;
					adi,obs-profile-rx-dec5-decimation = <0x5>;
					adi,obs-profile-rx-fir-decimation = <0x1>;
					adi,tx-profile-dac-div = <0x1>;
					adi,tx-profile-iq-rate_khz = <0x3c000>;
					adi,tx-profile-primary-sig-bandwidth_hz = <0x47868c0>;
					adi,tx-profile-rf-bandwidth_hz = <0xbebc200>;
					adi,tx-profile-thb1-interpolation = <0x2>;
					adi,tx-profile-thb2-interpolation = <0x1>;
					adi,tx-profile-tx-bbf-3db-corner_khz = <0x186a0>;
					adi,tx-profile-tx-dac-3db-corner_khz = <0x2e425>;
					adi,tx-profile-tx-fir-interpolation = <0x1>;
					adi,tx-profile-tx-input-hb-interpolation = <0x1>;
					adi,sniffer-profile-adc-div = <0x1>;
					adi,sniffer-profile-en-high-rej-dec5 = <0x0>;
					adi,sniffer-profile-iq-rate_khz = <0x7800>;
					adi,sniffer-profile-rf-bandwidth_hz = <0x1312d00>;
					adi,sniffer-profile-rhb1-decimation = <0x2>;
					adi,sniffer-profile-rx-bbf-3db-corner_khz = <0x186a0>;
					adi,sniffer-profile-rx-dec5-decimation = <0x5>;
					adi,sniffer-profile-rx-fir-decimation = <0x4>;
					reset-gpios = <0x28 0x14 0x0>;
					test-gpios = <0x28 0x15 0x0>;
					sysref_req-gpios = <0x28 0x1a 0x0>;
					rx2_enable-gpios = <0x28 0x16 0x0>;
					rx1_enable-gpios = <0x28 0x17 0x0>;
					tx2_enable-gpios = <0x28 0x18 0x0>;
					tx1_enable-gpios = <0x28 0x19 0x0>;
					linux,phandle = <0x36>;
					phandle = <0x36>;
				};
			};

			axi-jesd204-tx@20000 {
				compatible = "adi,axi-jesd204-tx-1.0";
				reg = <0x20000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1c 0x0>;
				clocks = <0x2d 0x2e 0x2f>;
				clock-names = "s_axi_aclk", "device_clk", "lane_clk";
				adi,octets-per-frame = <0x2>;
				adi,frames-per-multiframe = <0x20>;
				adi,converter-resolution = <0xe>;
				adi,bits-per-sample = <0x10>;
				adi,converters-per-device = <0x4>;
				adi,control-bits-per-sample = <0x2>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd_tx_lane_clk";
				linux,phandle = <0x2a>;
				phandle = <0x2a>;
			};

			axi-jesd204-rx@30000 {
				compatible = "adi,axi-jesd204-rx-1.0";
				reg = <0x30000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1b 0x0>;
				clocks = <0x2d 0x30 0x31>;
				clock-names = "s_axi_aclk", "device_clk", "lane_clk";
				adi,octets-per-frame = <0x4>;
				adi,frames-per-multiframe = <0x20>;
				adi,converter-resolution = <0x10>;
				adi,bits-per-sample = <0x10>;
				adi,converters-per-device = <0x4>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd_rx_lane_clk";
				linux,phandle = <0x29>;
				phandle = <0x29>;
			};

			axi-jesd204-rx@40000 {
				compatible = "adi,axi-jesd204-rx-1.0";
				reg = <0x40000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1d 0x0>;
				clocks = <0x2d 0x32 0x33>;
				clock-names = "s_axi_aclk", "device_clk", "lane_clk";
				adi,octets-per-frame = <0x2>;
				adi,frames-per-multiframe = <0x20>;
				adi,converter-resolution = <0x10>;
				adi,bits-per-sample = <0x10>;
				adi,converters-per-device = <0x4>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd_rx_os_lane_clk";
				linux,phandle = <0x2b>;
				phandle = <0x2b>;
			};

			axi-ad9371-tx-xcvr@24000 {
				compatible = "adi,altera-adxcvr-1.00.a";
				reg = <0x24000 0x1000 0x26000 0x1000 0x28000 0x1000 0x29000 0x1000 0x2a000 0x1000 0x2b000 0x1000>;
				reg-names = "adxcvr", "atx-pll", "adxcfg-0", "adxcfg-1", "adxcfg-2", "adxcfg-3";
				clocks = <0x2c 0x1 0x2e>;
				clock-names = "ref", "link";
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_tx_lane_clock";
				linux,phandle = <0x2f>;
				phandle = <0x2f>;
			};

			axi-ad9371-rx-xcvr@34000 {
				compatible = "adi,altera-adxcvr-1.00.a";
				reg = <0x34000 0x1000 0x38000 0x1000 0x39000 0x1000>;
				reg-names = "adxcvr", "adxcfg-0", "adxcfg-1";
				clocks = <0x2c 0x1 0x30>;
				clock-names = "ref", "link";
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_rx_lane_clock";
				linux,phandle = <0x31>;
				phandle = <0x31>;
			};

			axi-ad9371-rx-os-xcvr@44000 {
				compatible = "adi,altera-adxcvr-1.00.a";
				reg = <0x44000 0x1000 0x48000 0x1000 0x49000 0x1000>;
				reg-names = "adxcvr", "adxcfg-0", "adxcfg-1";
				clocks = <0x2c 0x1 0x32>;
				clock-names = "ref", "link";
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_rx_os_lane_clock";
				linux,phandle = <0x33>;
				phandle = <0x33>;
			};

			axi-ad9371-tx-dma@2c000 {
				compatible = "adi,axi-dmac-1.00.a";
				reg = <0x2c000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1e 0x4>;
				#dma-cells = <0x1>;
				clocks = <0x34>;
				linux,phandle = <0x37>;
				phandle = <0x37>;

				dma-channel {
					adi,source-bus-width = <0x80>;
					adi,destination-bus-width = <0x80>;
					adi,type = <0x1>;
				};
			};

			axi-ad9371-rx-dma@3c000 {
				compatible = "adi,axi-dmac-1.00.a";
				reg = <0x3c000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x1f 0x4>;
				#dma-cells = <0x1>;
				clocks = <0x34>;
				linux,phandle = <0x35>;
				phandle = <0x35>;

				dma-channel {
					adi,source-bus-width = <0x40>;
					adi,destination-bus-width = <0x80>;
					adi,type = <0x0>;
				};
			};

			axi-ad9371-rx-os-dma@4c000 {
				compatible = "adi,axi-dmac-1.00.a";
				reg = <0x4c000 0x4000>;
				interrupt-parent = <0x2>;
				interrupts = <0x0 0x20 0x4>;
				#dma-cells = <0x1>;
				clocks = <0x34>;
				linux,phandle = <0x38>;
				phandle = <0x38>;

				dma-channel {
					adi,source-bus-width = <0x40>;
					adi,destination-bus-width = <0x80>;
					adi,type = <0x0>;
				};
			};

			axi-ad9371-rx-hpc@50000 {
				compatible = "adi,axi-ad9371-rx-1.0";
				reg = <0x50000 0x8000>;
				dmas = <0x35 0x0>;
				dma-names = "rx";
				spibus-connected = <0x36>;
			};

			axi-ad9371-tx-hpc@54000 {
				compatible = "adi,axi-ad9371-tx-1.0";
				reg = <0x54000 0x4000>;
				dmas = <0x37 0x0>;
				dma-names = "tx";
				clocks = <0x36 0x2>;
				clock-names = "sampl_clk";
				spibus-connected = <0x36>;
				adi,axi-pl-fifo-enable;
				plddrbypass-gpios = <0x28 0x1c 0x0>;
			};

			axi-ad9371-rx-obs-hpc@58000 {
				compatible = "adi,axi-ad9371-obs-1.0";
				reg = <0x58000 0x1000>;
				dmas = <0x38 0x0>;
				dma-names = "rx";
				clocks = <0x36 0x1>;
				clock-names = "sampl_clk";
			};

			altera-a10-fpll@25000 {
				compatible = "altr,a10-fpll";
				reg = <0x25000 0x1000>;
				clocks = <0x2c 0x1>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_tx_link_clock";
				linux,phandle = <0x2e>;
				phandle = <0x2e>;
			};

			altera-a10-fpll@35000 {
				compatible = "altr,a10-fpll";
				reg = <0x35000 0x1000>;
				clocks = <0x2c 0x1>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_rx_link_clock";
				linux,phandle = <0x30>;
				phandle = <0x30>;
			};

			altera-a10-fpll@45000 {
				compatible = "altr,a10-fpll";
				reg = <0x45000 0x1000>;
				clocks = <0x2c 0x1>;
				#clock-cells = <0x0>;
				clock-output-names = "jesd204_rx_os_link_clock";
				linux,phandle = <0x32>;
				phandle = <0x32>;
			};
		};
	};

	a10leds {
		compatible = "gpio-leds";

		a10sr_led0 {
			label = "a10sr-led0";
			gpios = <0x39 0x0 0x1>;
		};

		a10sr_led1 {
			label = "a10sr-led1";
			gpios = <0x39 0x1 0x1>;
		};

		a10sr_led2 {
			label = "a10sr-led2";
			gpios = <0x39 0x2 0x1>;
		};

		a10sr_led3 {
			label = "a10sr-led3";
			gpios = <0x39 0x3 0x1>;
		};
	};

	clocks {

		sys_clk {
			#clock-cells = <0x0>;
			compatible = "fixed-clock";
			clock-frequency = <0x5f5e100>;
			clock-output-names = "system_clock";
			linux,phandle = <0x2d>;
			phandle = <0x2d>;
		};

		dma_clk {
			#clock-cells = <0x0>;
			compatible = "fixed-clock";
			clock-frequency = <0xee6b280>;
			clock-output-names = "dma_clk";
			linux,phandle = <0x34>;
			phandle = <0x34>;
		};

		clock@0 {
			#clock-cells = <0x0>;
			compatible = "fixed-clock";
			clock-frequency = <0xbb8000>;
			clock-output-names = "ad9371_ext_refclk";
		};
	};
};

For testing with different frame sizes, here are my findings:

With a Tx cyclic frame size of 3072

Rx Frame Size
4000 - no corrupt frame
4100 - no corrupt frame
3072*2 - corrupt frame observed 
8000 - corrupt frame observed

With a Tx cyclic frame size of 6144

Rx frame tested
4000 - no corrupt frame
4100 - no corrupt frame
6144 - corrupt frame observed 
8000 - corrupt frame observed

As suspected, the problem is most likely is independent of the transmitter frame size

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Arria10 AD9371: Bad Tx frame sent from SW when Rx/Tx sampling rates differ