AD-FMCDAQ2-EBZ on VC707 problem

Hi,

i have a problem with the AD-FMCDAQ2-EBZ on Xilinx VC707, short description:

  • make capture outputs the same data for terminated ADC inputs and DAC -> ADC loopback
  • SDK project get's SPI errors (AD9523: SPI write-verify failed (0x605) / AD9680: Invalid CHIP ID (0x4))

Detailed description:

Development-System Ubuntu 16.04
Vivado / SDK Version 2017.4
Development-Board Xilinx VC707
Evaluation-Board AD-FMCDAQ2-EBZ Rev. E on VC707 FMC1-HPC
Operationsystem-Type NO-OS
Processor MICROBLAZE

Source folder structure:

~/.../analog_jesd/app-manual [SDK workspace]
~/.../analog_jesd/hdl         [HDL Git folder: master branch]
~/.../analog_jesd/no-OS       [no-OS Git folder: master branch]

Build steps for HDL:

/.../analog_jesd/hdl/projects/daq2/vc707/make [build successful]

Build steps for no-OS:

Edit config.h [uncomment #define XILINX and #define MICROBLAZE]
/.../analog_jesd/no-OS/fmcdaq2/vc707/make log_make @ codepad
/.../analog_jesd/no-OS/fmcdaq2/vc707/make run log_make-run @ codepad
/.../analog_jesd/no-OS/fmcdaq2/vc707/make capture log_make-capture @ codepad

SDK.log @ codepad

Test 1: DAC outputs connected with ADC inputs

capture_ch1_loopback.csv
capture_ch2_loopback.csv

Test 2: ADC inputs terminated

capture_ch1_terminated.csv
capture_ch2_terminated.csv

The results of test1 and test2 are identical, i would expect  different results for loopback and terminated inputs!

 

Build steps for manual SDK project:

Workspace: ~/.../analog_jesd/app-manual
File->New Application Project->new Hardware Plattform(~/.../analog_jesd/hdl/projects/daq2/vc707/daq2_vc707.sdk)
Import all files (from ~/.../analog_jesd/no-OS/fmcdaq2/vc707/sw/src) into project src directory
Edit lscript.ld [change Heap Size to 0x100000]
Build successful

Debug steps for manual SDK project:

Create Debug Configuration [Xilinx C/C++ application (System Debugger), Standalone Application Debug, Local]
Debug

SDK-Terminal-Output:

Connected to /dev/ttyUSB0 at 115200
Available sampling rates:
  1 - ADC 1000 MSPS; DAC 1000 MSPS
  2 - ADC  500 MSPS; DAC 1000 MSPS
  3 - ADC  500 MSPS; DAC  500 MSPS
  4 - ADC  600 MSPS; DAC  600 MSPS
  5 - ADC 1000 MSPS; DAC 2000 MSPS (2x interpolation)
choose an option [default 1]:
1 - ADC 1000 MSPS; DAC 1000 MSPS
AD9523: SPI write-verify failed (0x605)!

AD9680: Invalid CHIP ID (0x4).
xcvr_setup ERROR: XCVR initialization failed!
xcvr_setup ERROR: XCVR initialization failed!
ad9144_setup : Invalid CHIP ID (0x4).
Tx link is disabled
Measured Link Clock: off
External reset is deasserted
Rx link is disabled
Measured Link Clock: off
External reset is deasserted
adc_setup adc core Status errors.
dac_setup DAC Core Status errors.

I have build everything like described in the tutorial but can't get the project running.

Can anybody help me or knows what the problem is?

Regards,

Andreas



added branch information
[edited by: ansc at 11:55 AM (GMT -4) on 19 Sep 2018]
Parents
  • 0
    •  Analog Employees 
    on Sep 19, 2018 12:41 PM

    Hi,

    The SPI seems to be messed up, You are running the 2018_r1 release for both no-Os and hdl right?


    Because the system is not initialize correctly you are not reading data captured by daq2, it is some data from the RAM.


    I will take a look into this and come up with a solution. Regarding this, can you use the master, when I have a resolution or is your flow fixed to 2018_r1 tools?

    Andrei

  • Hi,

    thanks for your help!

    You are right, the problem seems to be in the SPI part. The SPI read function seems to return the address it should read.

    I am running the master for both HDL and no-OS. Is this the 2018_r1?

    I will try to use the 2017_r1 tag now.

    I'm not fixed to this flow, i can also use Vivado and SDK 2016.4.

    Which would you recommend?

    Andreas

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