SYSREF problem when using AD9371 board and Zynq Ultrascale+ ZCU102

Dear all,

I have used board AD9371 with Zynq ZCU102. However, I want to connect AD9371 to ZCU102 via FMC HPC1 instead of FMC HPC0 as in the reference design (hdl_2018_r1)

Because HPC1 does not have "FMC_HPC0_LA33_P" and "FMC_HPC0_LA33_N" so we cannot use FPGA_SYSREF (channel 4) from AD9528 (as the top picture).

Then, I have to make some modifications (as the bottom picture)

- First of all, I configure "FPGA_AUX_CLK" (channel 3) of AD9528 as the new FPGA_SYSREF (with the same parameters of the original one)

- Secondly, since "FPGA_AUX_CLK" is connected to  "FMC_HPC_GBTCLK0_M2C" in FPGA, I have to route this signal through IBUFDS_GTE  (ODIV)  --> BUFG_GT --> JESD204B.

As I understand, FPGA_AUX_CLK is designed as DEV_CLK for JESD204B TX core, but in the end, this clock is unused since both JESD204B TX and RX CORE use FPGA_REF_CLK. That why I used it as an replacement of SYSREF.

However, the system with this configuration did not work. It's failed from ILA stage. Here is the log:

    9.337956] WARNING: 136: Mismatch detected in MYKONOS_jesd204bIlasCheck()
[    9.344755] ad9371 spi1.1: ILAS mismatch: c7f8
[    9.349181] ad9371 spi1.1: ILAS lanes per converter did not match
[    9.355257] ad9371 spi1.1: ILAS scrambling did not match
[    9.360551] ad9371 spi1.1: ILAS octets per frame did not match
[    9.366368] ad9371 spi1.1: ILAS frames per multiframe did not match
[    9.372618] ad9371 spi1.1: ILAS number of converters did not match
[    9.378782] ad9371 spi1.1: ILAS sample resolution did not match
[    9.384685] ad9371 spi1.1: ILAS control bits per sample did not match
[    9.391109] ad9371 spi1.1: ILAS bits per sample did not match
[    9.396838] ad9371 spi1.1: ILAS checksum did not match

Could you guys help me to clarify this error? Or is there any way to work around with HPC1 on ZCU102?