AXI_ADCFIFO IP was not worked OK with custom xc7z100-2ffg900I Board

We are doing a project which uses 5 ad9250bcpz-250 in our base board . And we have a Main core board which has two 32bit 1GB DDR3 connected to PS7 and two 32bit 1GB DDR3 connected to PL. Similar to xilinx ZC706 board(64bit 1GB DDR3 SODIMM connected to PL).

We had tested the 10 channels 250Msps ADC with adi JESD204 IP,util_adcfifo IP and the stream DMA IP, we send the 10 channels to MATLAB , it was tested OK.
But we want to record more samples in our project, about 512MB, now, We come across some problems.

1.The HP port width of zynq is 64bit and the normal clk frequency is 200M , we think this throughput can not handle our 10 channels 250Msps adc throughput (in fact ,we data pack 16 channels and the other 6 channels we padding all 0 data).

2.We also tested util_adcfifo IP and stream DMA IP, we data pack 16 channels to MATLAB (the other 6 channels padding all 0 data),it was tested OK, but it has only 32768 points per channel,this is limited by FPGA block ram resources.

3.Reference to ADI fmcdaq2,fmcadc2 projects, we port the adi axi_adcfifo IP connected to PL DDR3 and stream DMA IP, the DDR3 clock is running 800M. But we find the axi_adcfifo IP can not worked. This is our configuration below.
does anyone can help us ?