We are doing a project which uses 5 ad9250bcpz-250 in our base board . And we have a Main core board which has two 32bit 1GB DDR3 connected to PS7 and two 32bit 1GB DDR3 connected to PL. Similar to xilinx ZC706 board(64bit 1GB DDR3 SODIMM connected to PL).
We had tested the 10 channels 250Msps ADC with adi JESD204 IP,util_adcfifo IP and the stream DMA IP, we send the 10 channels to MATLAB , it was tested OK.But we want to record more samples in our project, about 512MB, now, We come across some problems.
1.The HP port width of zynq is 64bit and the normal clk frequency is 200M , we think this throughput can not handle our 10 channels 250Msps adc throughput (in fact ,we data pack 16 channels and the other 6 channels we padding all 0 data).
2.We also tested util_adcfifo IP and stream DMA IP, we data pack 16 channels to MATLAB (the other 6 channels padding all 0 data),it was tested OK, but it has only 32768 points per channel,this is limited by FPGA block ram resources.
3.Reference to ADI fmcdaq2,fmcadc2 projects, we port the adi axi_adcfifo IP connected to PL DDR3 and stream DMA IP, the DDR3 clock is running 800M. But we find the axi_adcfifo IP can not worked. This is our configuration below.does anyone can help us ?
Can you give us more details regarding what exactly is not working ?
Was the PL DDR tested in other applications, and you know it works correctly? Does the final design pass timing ?
Do you use Linux or No-Os for testing ?
Thanks very much for your immediate reply.
1. We use Linux and the zynq soc is booted with Micro SD card.
2. We tested the 32bit 1GB PL DDR3 with Xilinx axi virtual fifo controller ip . The main flow diagram is
JESD204_AD9250------2 channels DATA PACK ------- AXI FIFO GENERATOR-------AXI VIRTUAL FIFO IP WITH PL DDR3-----
ADI AXI STREAM DMA IP. We send the data through Ethernet and test in MATLAB . We get the data what the function generator does. But the Xilinx Virtual fifo IP has its limitations . We do not test the PL DDR3 in No-os application.
Does this test can prove the PL DDR3 is OK?
3.We replace the axi fifo generator IP and axi virtual fifo ip with adi axi_adcfifo ip and send the data to MATLAB to analyze.
But the data is not relevant to input signal.Because we test in linux ,and we do not go in detail with JTAG to debug the FPGA logic and timing.
Can you give us some suggestions to test ?
Below is our test pictures ,we are looking forward to your help. Thanks.
4、Xilinx AXI virtual fifo ip with PL DDR3 block diagram
5、xilinx axi virtual fifo ip with PL DDR3 test data in MATLAB
it can show more chan 200000 samples we take a part of them to show
6、axi_adcfifo ip with PL DDR3 block diagram
7、axi_adcfifo ip with PL DDR3 test data in MATLAB
The two designs had passed timing.Below is the picture after implementation.
Hello,Your test proves that the DDR physical interface works.In the configuration you've sent in the previous post, your AXI_ADC data width is configured. AXI_ADC/AXI and DMA data width should be matched between source and destination.Regards,Adrian
If your AXI Memory Mapped interface width is 256 bits, the axi_size should be set to 5.
Can you reconfigure the IP and retest your design?