FPGA Reference Designs

Q&A

by oldeng FPGA Reference Designs

Latest 1 day ago by PaulPG
321 7 0
Not Answered
AD7768 dma question 0
Not Answered

hello everyone , I have a desire to capture 8-chanel 128K 24bit ADC data and transfer or storage the data. I hope the data remains continuous and lossless. I have ported zedboard+ad7768's eval project and succesfull run it...

Analog to Digital Converters (ADCs) software ad7768 reference design

321 7 0
by Danial25548 FPGA Reference Designs

Latest 7 days ago by Cristianmihaipopa1601
418 5 0
Not Answered
Using PL Ethernet on AX7350B + ADRV9002 for high-rate IQ streaming with srsRAN 0
Not Answered

Hi everyone, I am working with an Alinx AX7350B + ADRV9002 platform. I have successfully ported the zc706-adrv9002 design and integrated it with my srsRAN LTE project. At the moment, the IQ data is transferred between the host and the board through...

hardware ADRV9002 software defined radio rf and microwave

418 5 0
by someusername FPGA Reference Designs

Latest 7 days ago by Cristianmihaipopa1601
323 6 0
Suggested Answer
AD9081 Reference Design on VCK190 with custom Parameters 0
Suggested Answer

Hello, I tried to build the VCK190 reference design for the AD9081 with custom parameters. The command used: make JESD_MODE=8B10B REF_CLK_RATE=122.88 RX_JESD_L=2 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 RX_LANE_RATE=4.9152 TX_JESD_L=2 TX_JESD_M=4 TX_JESD_S...

hardware A/D and D/A Converter Combinations jesd204b AD9081+VCK190 AD9081_FMCA_EBZ Show More

323 6 0
by SongSunHah FPGA Reference Designs

Latest 7 days ago by Cristianmihaipopa1601
211 2 0
Not Answered
QSFP Driver Support 0
Not Answered

Hi, I am testing the QSFP function of ADRV9009-ZU11EG+ADRV2CRR-FMC, but in the description of HDL project: https://github.com/analogdevicesinc/hdl/tree/main/projects/adrv9009zu11eg/adrv2crr_fmc , the device tree file seems that has been removed,: zynqmp...

software 2022 adrv9009 software defined radio ADRV9009-ZU11EG rf and microwave Show More

211 2 0
by Sidra2026 FPGA Reference Designs

Latest 7 days ago by Cristianmihaipopa1601
270 2 0
Not Answered
ADRV9009 JESD204B Testbench Build Issues on ZCU102 — HDL 2022_R2 0
Not Answered

I am building the HDL and testbench repositories for the JESD204B interface framework targeting the ADRV9009 project on the ZCU102 evaluation board. HDL Repository The HDL repository has been built successfully using tag version 2022_R2 . Reference...

Vivado 2022.2 software ADRV9009-ZCU102 testbench software defined radio High Speed A/D Converters >10 MSPS rf and microwave Show More

270 2 0
by tchrist FPGA Reference Designs

Latest 8 days ago by ADIrobertADI
590 10 0
Not Answered
JESD204B TX problem 0
Not Answered

Hello, We are having some trouble with the tx path using a JESD204B link with AD9371 and FPGA (error 0x61). We have been probing a bit on the FPGA with ILA-cores and have found that the ILAS_config_data, ILAS_config_rd, and ILAS_config_addr is behaving...

hardware jesd204b software defined radio rf and microwave fpga Show More

590 10 0
by VICKY1 FPGA Reference Designs

Latest 8 days ago by ADIrobertADI
630 8 0
Not Answered
Change Hdl design clk rates 0
Not Answered

Hello Everyone , Actually i have a doubt in adrv9001_zcu102 project i want to set util_dac , util_adc , tx2_dma , rx2_dma clock rates for my convenience so that i can work according with my pl and work at the rate which i required how can i change it...

software VIVADO 2022.1 ADRV9002 fpga reference design Wideband Transceiver IC RF Integrated Transceivers adrv9001 zcu102 reference design Show More

630 8 0
by milosoftware FPGA Reference Designs

Latest 8 days ago by milosoftware

149 2 0

Not Answered
AD9083 on speed grade -1 0
Not Answered

We're evaluating the AD8093 for a new design, so we attached the AD9083EBZ to our custom board (i.o.w. not the zcu102). The MPSoC is also a ZU9. I've ported the reference design for the zcu102 to our system, and that now works and produces data. There...

Analog to Digital Converters (ADCs) AD9083EBZ software AD9083

149 2 0
by oldeng FPGA Reference Designs

Latest 10 days ago by Stanca
122 1 0
Not Answered
ad7768 only one channel have data 0
Not Answered

I have design a custom board with zynq020 + ad7768 I have succesfull ported hdl and no-os example. and when I run iio demo . the iio scope show only one channel have real data,and the others is constant value. my crystal is 24mhz, here is my schematic...

Analog to Digital Converters (ADCs) software Vivado 2022 ad7768

122 1 0
by yhkim

FPGA Reference Designs

Latest 14 days ago by yhkim
237 2 0
Answered
BOOT.BIN for AD9084 running on VCK190 +1
Answered

Hello, I'm trying to build HDL for AD9084 and VCK190 by following the instructions from here: analogdevicesinc.github.io/.../versal.html . I can build the HDL and generate system_top.xsa without an issue, but I have a difficulty in generating BOOT.BIN...

software A/D and D/A Converter Combinations AD9084 Vivado 2025.1

237 2 0
by milosoftware FPGA Reference Designs

Latest 22 days ago by TudorTicudean
287 4 0
Answered
AD9083EBZ buzzing noise when powered +1
Answered

We're evaluating the AD8093 for a new design, so we attached the AD9083EBZ to our custom board (i.o.w. not the zcu102). This board so far worked fine with any FMC add-on we've used. When I plug the AD9083EBZ into the FMC and power-on the system, it...

Analog to Digital Converters (ADCs) AD9083EBZ hardware High Speed A/D Converters >10 MSPS AD9083 Show More

287 4 0
by milosoftware FPGA Reference Designs

Latest 22 days ago by TudorTicudean
292 4 0
Answered
Inferred bus interface 'S_AXI' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories) +1
Answered

I'm building a design using the AD9083. I built the reference design for the EVM and now want to move that to our custom board. When I add my custom RTL code to the project, I get this message from Vivado 2025.1: INFO: [IP_Flow 19-5107] Inferred bus...

Analog to Digital Converters (ADCs) software vivado hdl AD9083 Show More

292 4 0
by Socchiplet FPGA Reference Designs

Latest 23 days ago by AlexSarbu
609 7 0
Answered
ADRV9029 with ZCU102 carrier +1
Answered

Hi, Can you please provide raw IQ data capture example for ADRV9029 with ZCU102 carrier for your HDL design and no-OS setup. I am trying to transmit some waveform and then do a loop back and want to use adrv9029 observation path. I am using Vivado...

software ADRV9029 software defined radio Wideband Transceiver IC rf and microwave RF Integrated Transceivers Show More

609 7 0
by Kalpataru FPGA Reference Designs

Latest 23 days ago by Kalpataru

506 9 0

Not Answered
Timing Failure (WHS) in AD9361 Reference Design - Vivado 2025.1 - ZC702/706 0
Not Answered

I am seeing a Hold Time Violation (WHS) when using the latest ADI reference HDL for the AD9361 on both ZC702 and ZC706. Despite using default strategies and attempting Performance-based strategies, the design consistently fails timing in the rx_clk domain...

hdl reference design software zc706 zc702 ad9361 software defined radio vivado2025.1 fmcomms2 rf and microwave Show More

506 9 0
by Nabonit FPGA Reference Designs

Latest 24 days ago by TudorG
271 3 0
Answered
AD-FMCDAQ2-EBZ on VC709: MicroBlaze silently hangs at ad9523_setup() (AXI SPI timeout), causing ILA clock stopped error +1
Answered

Hardware Setup: Carrier Board: Xilinx VC709 (MicroBlaze soft processor design) FMC Card: AD-FMCDAQ2-EBZ (connected to the HPC1 slot) External Clocks: None. I am using the standard ADI reference design and relying entirely on the default...

hardware Clock ICs clock and timing noos vc709 microblaze ad9523-1 High Speed A/D Converters >10 MSPS daq2 ad-fmcdaq2-ebz Show More

271 3 0

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Q&A

Not Answered
AD7768 dma question 0
Not Answered

Not Answered
Using PL Ethernet on AX7350B + ADRV9002 for high-rate IQ streaming with srsRAN 0
Not Answered

Suggested Answer
AD9081 Reference Design on VCK190 with custom Parameters 0
Suggested Answer

Not Answered
QSFP Driver Support 0
Not Answered

Not Answered
ADRV9009 JESD204B Testbench Build Issues on ZCU102 — HDL 2022_R2 0
Not Answered

Not Answered
JESD204B TX problem 0
Not Answered

Not Answered
Change Hdl design clk rates 0
Not Answered

Not Answered
AD9083 on speed grade -1 0
Not Answered

Not Answered
ad7768 only one channel have data 0
Not Answered

Answered
BOOT.BIN for AD9084 running on VCK190 +1
Answered

Answered
AD9083EBZ buzzing noise when powered +1
Answered

Answered
Inferred bus interface 'S_AXI' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories) +1
Answered

Answered
ADRV9029 with ZCU102 carrier +1
Answered

Not Answered
Timing Failure (WHS) in AD9361 Reference Design - Vivado 2025.1 - ZC702/706 0
Not Answered

Answered
AD-FMCDAQ2-EBZ on VC709: MicroBlaze silently hangs at ad9523_setup() (AXI SPI timeout), causing ILA clock stopped error +1
Answered

Q&A

Not Answered AD7768 dma question 0 Not Answered

Not Answered Using PL Ethernet on AX7350B + ADRV9002 for high-rate IQ streaming with srsRAN 0 Not Answered

Suggested Answer AD9081 Reference Design on VCK190 with custom Parameters 0 Suggested Answer

Not Answered QSFP Driver Support 0 Not Answered

Not Answered ADRV9009 JESD204B Testbench Build Issues on ZCU102 — HDL 2022_R2 0 Not Answered

Not Answered JESD204B TX problem 0 Not Answered

Not Answered Change Hdl design clk rates 0 Not Answered

Not Answered AD9083 on speed grade -1 0 Not Answered

Not Answered ad7768 only one channel have data 0 Not Answered

Answered BOOT.BIN for AD9084 running on VCK190 +1 Answered

Answered AD9083EBZ buzzing noise when powered +1 Answered

Answered Inferred bus interface 'S_AXI' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories) +1 Answered

Answered ADRV9029 with ZCU102 carrier +1 Answered

Not Answered Timing Failure (WHS) in AD9361 Reference Design - Vivado 2025.1 - ZC702/706 0 Not Answered

Answered AD-FMCDAQ2-EBZ on VC709: MicroBlaze silently hangs at ad9523_setup() (AXI SPI timeout), causing ILA clock stopped error +1 Answered

Not Answered
AD7768 dma question 0
Not Answered

Not Answered
Using PL Ethernet on AX7350B + ADRV9002 for high-rate IQ streaming with srsRAN 0
Not Answered

Suggested Answer
AD9081 Reference Design on VCK190 with custom Parameters 0
Suggested Answer

Not Answered
QSFP Driver Support 0
Not Answered

Not Answered
ADRV9009 JESD204B Testbench Build Issues on ZCU102 — HDL 2022_R2 0
Not Answered

Not Answered
JESD204B TX problem 0
Not Answered

Not Answered
Change Hdl design clk rates 0
Not Answered

Not Answered
AD9083 on speed grade -1 0
Not Answered

Not Answered
ad7768 only one channel have data 0
Not Answered

Answered
BOOT.BIN for AD9084 running on VCK190 +1
Answered

Answered
AD9083EBZ buzzing noise when powered +1
Answered

Answered
Inferred bus interface 'S_AXI' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories) +1
Answered

Answered
ADRV9029 with ZCU102 carrier +1
Answered

Not Answered
Timing Failure (WHS) in AD9361 Reference Design - Vivado 2025.1 - ZC702/706 0
Not Answered

Answered
AD-FMCDAQ2-EBZ on VC709: MicroBlaze silently hangs at ad9523_setup() (AXI SPI timeout), causing ILA clock stopped error +1
Answered