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Frequently Asked
QPLL support in axi_adxcvr and util_adxcvr
Answered
over 1 year ago
Designing with multiple ADRV9009 chips
Answered
over 1 year ago
ADRV9009 JESD Error
Answered
over 1 year ago
[ADRV9009 + ZCU102] No-OS Receive data showing up as 0s.
Answered
10 months ago
ad9361 digital loop back
Answered
11 months ago
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ADRV9009/ZCU102 FPGA Reference Design Clocks
0
3
views
0
replies
on 20 Jan 2020
by
AJohn941
Suggested Answer
FMCJESDADC: Problems with PN23 seq check
0
818
views
22
replies
on 20 Jan 2020
by
matianyi@tsinghua.edu.cn
Not Answered
ADRV9009-ZU11EG SOM util_som_rx_cpack data interweave format
0
92
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7
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on 18 Jan 2020
by
CsomI
Not Answered
Can't Build Projects Using Makefile
0
57
views
6
replies
on 18 Jan 2020
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CsomI
Answered
the block design of ad9371
0
112
views
5
replies
on 18 Jan 2020
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fly_lin
Answered
can i make fmcomms4 as wifi router
0
280
views
17
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on 18 Jan 2020
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Not Answered
daq2 reference design AD-FMCDAQ2-EBZ with Xilinx ZC706
0
63
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5
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on 17 Jan 2020
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AdrianC
Not Answered
ad9361 data clock division w/o fifo
0
20
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1
reply
on 17 Jan 2020
by
andrei_g
Answered
ADRV9361-Z7035 noise on the output
0
39
views
1
reply
on 16 Jan 2020
by
travisfcollins
Not Answered
error in installation of communication system toolbox for zynq based radio in matlab
0
54
views
6
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on 16 Jan 2020
by
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Answered
BOM list of ADRV9361-Z7035
0
29
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2
replies
on 16 Jan 2020
by
mertsalar
Not Answered
AD-FMCDAQ2-EBZ axi_ad9680_core IP core documentation
0
22
views
1
reply
on 16 Jan 2020
by
andrei_g
Not Answered
Error with generate HDL project
0
43
views
2
replies
on 15 Jan 2020
by
DiegoVelayarce
Suggested Answer
AXI I2S on Ultrascale
0
180
views
11
replies
on 15 Jan 2020
by
btogorean
Answered
Processing the ORX data stream in adrv9009_zcu102
0
56
views
3
replies
on 15 Jan 2020
by
EHeinz689
Answered
Adding Xilinx ILA to a reference design
0
46
views
2
replies
on 15 Jan 2020
by
EHeinz689
Not Answered
ADI DMAC with 64bit address.
0
22
views
1
reply
on 15 Jan 2020
by
lnagy
Answered
Unexpected Received Chirp Attenuation
0
139
views
15
replies
on 13 Jan 2020
by
pjfiske
Answered
ad9361 HDL on TRENZ ultrascale
0
54
views
2
replies
on 13 Jan 2020
by
mmilosavljevic
Answered
Using VHDL in HDL reference designs
0
48
views
2
replies
on 13 Jan 2020
by
EHeinz689
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