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FPGA Reference Designs
FPGA Reference Designs

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FPGA Reference Designs requires membership for participation - click to join
Frequently Asked
  • rmd91
    Designing with multiple ADRV9009 chips
    Answered 4 months ago
  • jwil
    QPLL support in axi_adxcvr and util_adxcvr
    Answered 4 months ago
  • sqc_psg
    AD9361 HDL - Inserting a FFT into the block design
    Answered 5 months ago
  • Noob
    Regarding modifying HDL reference file
    Answered 2 months ago
  • DrMurad
    ad9361 digital loop back
    Answered 1 month ago
  • Not Answered

    "clkout_in" in the ad9361 hdl driver 0

    20 views
    1 reply
    on 22 Mar 2019 by andrei_g
    •  Analog Employees 
  • Suggested Answer

    我想用ADF7021 作为发射接收数传电路 0

    30 views
    2 replies
    on 22 Mar 2019 by andrei_g
    •  Analog Employees 
  • Not Answered

    FMCDAQ2 pass AD9680 data to AD9144 output 0

    98 views
    3 replies
    on 22 Mar 2019 by sdavistech
  • Answered

    ADRV9009+Zynq3 (or ZC706) 0

    81 views
    2 replies
    on 22 Mar 2019 by siran
  • Not Answered

    AD9467FMC250M &ZedBoard Problem with no-OS project 0

    228 views
    12 replies
    on 21 Mar 2019 by SaWick
  • Not Answered

    ADRV9361-z7035 SOM clocks with adrv1crr-fmc 0

    37 views
    2 replies
    on 21 Mar 2019 by andrei_g
    •  Analog Employees 
  • Not Answered

    [ZCU102 + ADRV9009] What are the root causes of "Deframer Status 0x13 and Framer Status 0x67" 0

    119 views
    5 replies
    on 21 Mar 2019 by mhennerich
    •  Analog Employees 
  • Not Answered

    AD9361 streaming data direct to console, bypassing the DMA 0

    161 views
    8 replies
    on 21 Mar 2019 by andrei_g
    •  Analog Employees 
  • Answered

    ADRV9364 HDL optimization 0

    97 views
    4 replies
    on 20 Mar 2019 by oclabbao
  • Not Answered

    How to set BBPLL Fref value? 0

    70 views
    3 replies
    on 20 Mar 2019 by DragosB
    •  Analog Employees 
  • Answered

    motcon2_fmc HDL 0

    46 views
    2 replies
    on 20 Mar 2019 by adiv
  • Not Answered

    Unable to Modify DAC Core Frequency ( KCU105 + FMCDAQ2 + Loopback ) using Vivado 18.2 0

    135 views
    6 replies
    on 20 Mar 2019 by andreid1994
    •  Analog Employees 
  • Suggested Answer

    integrating xilinx JESD core with zc706 no os project 0

    304 views
    19 replies
    on 19 Mar 2019 by AdrianC
    •  Analog Employees 
  • Not Answered

    DAC DMA Write and ADC read DATA plus garbage values 0

    89 views
    3 replies
    on 19 Mar 2019 by lnagy
    •  Analog Employees 
  • Not Answered

    AD9361 output error 0

    264 views
    9 replies
    on 19 Mar 2019 by huxiaoyu
  • Not Answered

    How do I reduce power consumption of ADRV9364-Z7020? 0

    77 views
    2 replies
    on 18 Mar 2019 by EdwardK
  • Not Answered

    axi_ad9361 ip core - sync_in signal 0

    32 views
    1 reply
    on 18 Mar 2019 by travisfcollins
    •  Analog Employees 
  • Suggested Answer

    ZC706 + ADRV9009 clock rx_clkgen: MMCM-PLL NOT locked 0

    68 views
    3 replies
    on 18 Mar 2019 by lnagy
    •  Analog Employees 
  • Answered

    DAQ2 ZC706 Reference Design axi_ad9144_jesd output data format 0

    136 views
    6 replies
    on 18 Mar 2019 by andrei_g
    •  Analog Employees 
  • Not Answered

    2 AD design for 4X4 MIMO +1

    69 views
    2 replies
    on 18 Mar 2019 by andrei_g
    •  Analog Employees 
>
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