Just a comment, maybe a way to improve things in the new year. I had a customer recently who was working with the FPGA design documents that we provide to design a JESD interface for one of our high speed ADCs. He was able to get things working and was happy in the end, but suggested that, specifically in the FPGA code blocks, that we add more comments and a little more description on exactly what was going on. He told me that it would have saved him a good deal of time if he didn't need to spend so much time decoding our FPGA blocks. This customer is a very sharp guy, to his credit he was able to get his interface working.
take care all!
In generic terms, yes, we will do that and is a valid comment.
However in this case, I must add, is a disconnect between software and HDL.
A description of this is in here (which is stating the obvious in HDL of course), not sure if he really read all this (I doubt it).
Base (common to all cores) [Analog Devices Wiki]
The enable is a direct indication dac data select (if the source is external; in this case the loopback data). However, this information comes from how software interacts with the core. The document will always be generic and without a special case (hence refers it as external data). The software is what "configures" it to a particular use case (loopback data). That is best left to the user. The expected interpretation of this function is "IF you want to source your data for the DAC, software (or you may hardcode) must set "XYZ" on this register.
This is in no way a defense against your comment, which is very valid and we are working on it.
Just keeping expectations at the right level.