Trigger Signal Acquisition KC705 + AD-FMCJESDADC1-EBZ

Our system configuration is as follows:
KC705 with AD-FMC-JESD board.

HDL Version: R2018_r2

We are trying to add a one-bit trigger signal in the MSB of our ADC sampled data. Our approach is to use the trigger in SMA connector (TR port on AD-FMC-JESD) board to take a 1-bit input and add it to the MSB of the captured data. We used IBUFGDS modules to read the differential inputs from the board and connected them to system_wrapper.v module. The system_top.v, system_wrapper.v and constraint files are attached for reference.

We wrote a trigger module namely adc_trigger.v which is attached. The purpose of the attached adc_trigger module is to take the trigger signal from AD-FMC-JESD trigger input and add it to the MSB of the ADC data. We inserted our adc_trigger module between adc_core_0 and cpack packer. The screen shot is attached.

We used the attached no-OS ad_fmcjesdadc1_ebz.c file. The file initiates DMA and captures the ADC data with trigger.

Our test setup is as follows:
1. Sine wave of 5MHz on CH1.
2. a) A 0.5V peak 1MHz pulse wave with 30% duty cycle.
b) Open trigger pin (Nothing connected).

When we observed the captured output, it showed the correct sine wave in the 14 LSBs of the data. However, the trigger bit (the MSB of the adc data) has a pattern of 24 ones followed by 24 zeros. We expect lower number of ones and higher number of zeros at least as our duty cycle is only 30%. The same pattern exists for both the signals on the trigger pin (0.5 V peak pulse wave as well as open trigger pin). If the input voltage is too low to be regarded as 1, it should have shown an all zeros pattern, but it didn't.

We need guidance if we are doing something wrong in the whole process to get the trigger signal.

added tags
[edited by: sheikh fahad at 7:41 AM (GMT 0) on 24 Jan 2020]

Top Replies