Our system configuration is as follows:KC705 with AD-FMC-JESD board.HDL Version: R2018_r2NO-OS Version: MASTER
We are trying to add a one-bit trigger signal in the MSB of our ADC sampled data. Our approach is to use the trigger in SMA connector (TR port on AD-FMC-JESD) board to take a 1-bit input and add it to the MSB of the captured data. We used IBUFGDS modules to read the differential inputs from the board and connected them to system_wrapper.v module. The system_top.v, system_wrapper.v and constraint files are attached for reference.
We wrote a trigger module namely adc_trigger.v which is attached. The purpose of the attached adc_trigger module is to take the trigger signal from AD-FMC-JESD trigger input and add it to the MSB of the ADC data. We inserted our adc_trigger module between adc_core_0 and cpack packer. The screen shot is attached.
We used the attached no-OS ad_fmcjesdadc1_ebz.c file. The file initiates DMA and captures the ADC data with trigger.
Our test setup is as follows:1. Sine wave of 5MHz on CH1.2. a) A 0.5V peak 1MHz pulse wave with 30% duty cycle. b) Open trigger pin (Nothing connected).
When we observed the captured output, it showed the correct sine wave in the 14 LSBs of the data. However, the trigger bit (the MSB of the adc data) has a pattern of 24 ones followed by 24 zeros. We expect lower number of ones and higher number of zeros at least as our duty cycle is only 30%. The same pattern exists for both the signals on the trigger pin (0.5 V peak pulse wave as well as open trigger pin). If the input voltage is too low to be regarded as 1, it should have shown an all zeros pattern, but it didn't.
We need guidance if we are doing something wrong in the whole process to get the trigger signal.
Hi,Can you explain more your setup?1.2.a)b)
It is not clear for me.Do you capture with the ADC the "A 0.5V peak 1MHz pulse "Can you check with an ILA the captured ADC signals and the trigger signal? I see an input differential buffer for the trigger.You expect 30% of ones and 70% zeros. I expect 2% 1 and the rest of 98% zeros, you have a rising edge condition there, and temper with 2 samples per channel on each rising edge.
Thanks for your response.
I have applied a sine wave signal of 5 MHz frequency at Channel A0, with voltage 500 mVpp. and
A trigger pulse of frequency 1 MHz at the port TR of ad-fmcjesdadc1-ebz with 500 mVpp and 30% of duty cycle.As this trigger is available on pin G2 and G3 of HPC connector . which is trigger _p and trigger _n respectively. As interfaced in M2C project .Using these two pins we have places a differential buffer "IBUFGDS" to obtain a single bit of trigger.
You are right that at rising edge configuration we only get 2 sample in a trigger cycle. But in our module we have inserted the trigger bit in MSB of ADC 16 bit sample to evaluate the presence of trigger bit in each sample which should have 30% and 70% RATE of appearance of "1" and "0" respectively. but the results are same as in open TR port of adc card. Today i performed more test in which in ramp test there is all zero in 16th bit of stored samples. but when i apply an external signal to the ADC port without any signal at TR port the 16th bit has 0 in 24 sample and 1 in next 24 samples.The main issue i feel is that we have not configured the "TR" trigger port of adfmcjesdadc card.Kindly guide me the steps to properly configure the trigger port of Adfmcjesdadc1 card to get the 2% trigger bits in adc data.
Hi,Your trigger signal is too small, from the fmcjesdadc1 schematic:Check it with an ILA...Andrei
OK i will check , and kindly elaborate "ILA". thanks.
ILA = Integrated Logic AnalyzerYou can find a lot of documentation on Xilinx sites... forums about it.https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug936-vivado-tutorial-programming-debugging.pdfLong story short...
You can find it in the IP catalog. (Open the block design -> add IP -> chose ILA)Configure it. You need the native mode, not AXI. Connect a clock(max 250MHz) and your signal.Generate bitstream, recompile the SDK project(no-OS) with the obtained hdf. Run the program.From Vivado, open hardware manager -> open target -> auto-connect. You should see your ILA. Click on Run.Andrei