zed ADV7511 ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source

Hi

   I want to run the ADV7511 on my zedboard,and my vivado is 2018.3/2019.1.(https://wiki.analog.com/resources/fpga/xilinx/kc705/adv7511#dokuwiki__top )     Maybe this project is not support vivado 2019.1,so I try it on my vivado 2018.3.

  From https://ez.analog.com/fpga/f/discussions/103444/adv7511-reference-design-not-working-on-zedboard/307007#307007  and https://ez.analog.com/linux-device-drivers/f/q-a/109298/dmac_core-header-file-missing-for-adv5711-zedboard-reference-design   ,I found that I can only use 2018_r1 hdl and no-os, because the 2019_r1 doesn't have no-os branch and 2018_r2 no-os branch doesn't have dmac_core.h.  But when I source 2018_r1 , I have encountered the following problem.I can click the " run connection automation" button to connect them in vivado, but the TCL has stopped.

ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source
/axi_spdif_tx_core/s_axi_aclk
/axi_i2s_adi/s_axi_aclk

ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.

while executing
"validate_bd_design"
(procedure "adi_project_xilinx" line 100)
invoked from within
"adi_project_xilinx adv7511_zed"
(file "./system_project.tcl" line 8)

  Can you give me help? Solving the problem that 2018_r2 without dmac_core.h、config.h is also OK. In addition, this routine has a Linux system version?

Thanks.

ylh



1
[edited by: ylh at 11:16 AM (GMT 0) on 6 Aug 2019]