Wedeepika to RX1 internally by modifying the HDL code. I am assuming that in IP util_ad9371_tx_upack fifo_rd_data_0 and 1 represent the I and Q of TX1 and fifo_rd_data_2 and 3 represent the I and Q of TX2. Since all 4 ports are 32 bits so I tried assuming the data in LSB side 16 bits and to MSB side 16 bits, but didn't get the desired results. And i am assuming in ip util_ad9371_rx_cpack fifo_wr_data_0 and 1 represent the I and Q of RX1 and fifo_wr_data_2 and 3 represent the I and Q of RX2.
We are using C code in linux to transmit and receive data. Only TX1 and RX1 are enabled. So the data are written in the buffer in sequence (I1 Q1 I1 Q1 I1 Q1..............................) and read from in receiver buffer the same pattern.But if am writing sequence in in I and Q of TX1 (0 0 1 1 2 2 3 3 .........................) then i am receiving I= 0 0 2 2 4 4 6 6 , means repeated values with one jump.
To do internal loop back i have connected LSB 16 bit of fifo_rd_data_0 to fifo_wr_data_0 and LSB 16 bit of fifo_rd_data_1 to fifo_wr_data_1. I have tried with MSB 16 bit also but not getting same sequence as transmitted.
Please clear is this assumtions are correct?
moved to FPGA reference design community
Hi,The axi_ad9371 dma interface.
Please take a look at the above.If you disable one channel, the upack and cpack are there to use the maximum DMA/memory resources, not having to move zeros or junk data around. Meaning, fifo_rd_data_2 and 3 represent the I and Q of TX1 (t+1).I'm not sure what you changed in hdl and software. If you still have problems after going through the above documentation, give us more details about what is your goal and what have you changed.