Whether you're debugging a stubborn camera link or designing a robust system from scratch, knowing where errors hide is half the battle. GMSL provides a myriad of different types of errors to monitor. In this blog, we will discuss where in the signal chain these can occur.
We reviewed the GMSL channel in the previous post to reinforce the importance of adhering to the channel specification. We spent a whole blog post covering this topic because it is one of two regions where errors can occur. The beauty of GMSL is the simplicity, low latency, and low overhead needed for it to work.
The Open Systems Interconnection (OSI) Model
The OSI model abstracts all the different components of a communication system into different layers, which all serve unique functions to ultimately handle the transportation of the data.
GMSL, or SerDes, is a point-to-point topology that encapsulates only two of these layers in the device.
- The physical layer, sending and receiving the symbols over a physical medium like a cable.
- The data link layer, connecting the two devices and delivering error-free frames of data between the serializer and deserializer utilizing a specific protocol.
By simplifying the concept of a SerDes system, it allows us to narrow down the problems to two different portions of the link.
Figure 1: Location of the Physical and Data Link Layers in a SerDes System
The Physical Layer
Outside of the GMSL IC, the GMSL physical layer interfaces need to travel through a PCB, cable, and connectors from the source to the sink. The last blog post on channel specification was intended to enforce the importance of providing a robust channel for the GMSL signals to travel on.
We outline the transmission line requirements of 50 Ω for single-ended connections or 100 Ω for differential connections and needing to operate up to 3 GHz. However, there are no hard requirements for which PCB stackups, cables, or connectors can or cannot be used. This provides flexibility for the system designers to choose the components that work best for their application and then cross-check them against the channel specification.
We can help guide system designers with our comprehensive GMSL2 Hardware Design and Validation Guide.
Additionally, the routing of the source interface into the serializer and routing of the sink interface out from the deserializer also have their own guidelines. For the sake of this discussion, we assume those are adhered to.
The physical layer is the lowest layer and if signals cannot travel error-free across the link, nothing else downstream really matters. It is important to validate the signal integrity of the link before proceeding further into the IC.
The GMSL link cannot be considered in a vacuum though. A real-world application will have the cable routed next to other cables, near the presence of antennas and other radiators, through dynamically moving hinges, all while needing to operate over fluctuating temperatures—more reasons to focus on the physical layer issue sources first.
Figure 2: Examples of a Signal Travelling Through an Ideal (top) and Non-Ideal (bottom) Channel
The Data Link Layer
After validating a compliant GMSL channel (and ensuring compliance over worst-case conditions), we can look to focus on the inner workings of the GMSL chip itself.
The data link layer is considered one of the most complex layers of the interconnect model because it manages the conversion of the physical signals into the data protocol and abstracts the complexity of transceiving the data. It is also responsible for encapsulating the data into frames, error detection, error correction, flow control, and other features.
Errors occurring here are typically caused by incorrect configurations or miscalculation of bandwidths.
Two common examples are buffer overflows and cyclic redundancy check (CRC) errors.
A buffer overflow occurs when the device is receiving more data than it can output. If you are using a 6 Gbps GMSL2 device, that is the physical maximum amount of data that can be processed at one time. If the sensor is outputting at a rate of 8 Gbps, then there’s no way a 6 Gbps serializer device would be able to keep up, which leads to the buffer overflowing and frames being dropped.
Figure 3: Visualization of the FIFO Receiving and Transmitting the Data
A variety of CRCs used on the GMSL data channels quickly confirm the integrity of the received data. The transmitter creates a CRC based on the packet of data and the receiver runs the data through the same polynomial and compares the original CRC to the calculated CRC.
If there are no issues on the physical layer, then the likely cause is some misconfiguration on one end of the link leading to data missing or incorrectly routed.
Figure 4: A CRC is Generated from a Pseudorandom Polynomial
Conclusion
Even the best designs still have a chance for errors to occur, but reviewing the potential error sources should help you be proactive early, rather than reactive much later in the design. Understanding where errors lurk in the GMSL signal chain is essential for building reliable, high-performance systems. Armed with this knowledge, you're better equipped to design robust GMSL implementations, troubleshoot problems efficiently, and ensure your high-speed video and data links perform flawlessly in the field.
With all the high-level topics discussed, stay tuned as we describe some of the common errors in more detail to help you quickly diagnose any potential sources of errors.
See all the blogs in the GMSL Debugging series.