In this final blog of the Easy Drive ADC series, I take a deep dive into an ADC simulation, focusing on the AD4003 (18-Bit, 2 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADC) and AD4696 (16-Bit, 16-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC). Earlier blogs in this series covered high-level tools for product selection and evaluation. For instance, blog 6 in the series covered the evaluation capabilities of LTspice when choosing precision ADCs. This blog expands on that topic.
The starting point for any LTspice evaluation should be a simple circuit that runs quickly, giving the designer insight into the function of the circuit, and broadstroke feedback about component choices.
For instance, Figure 1 shows the AD4003 ADC in a minimal circuit, enough to reveal the timing of sampling, and how the ADC responds to input. As explained in an earlier blog, in LTspice, ADCs are modeled as analog signals in and analog out—as if an ideal DAC were used to convert the ADC’s output codes back to analog for the result. This reveals several important analog effects, including ADC front-end noise and switching, as well as output word quantization. Note that the digital signal, V(cnv) pulsed signal, is the Sample Convert (CNV) input, not the digital output clock. The I/O clock can be added for reference, but its timing is relative to the convert signal. Here, the I/O clock and digital data stream are not included as part of the model. The timing relationship between CNV and the I/O clock is a function of the design’s digital controller, and should be modelled separately.
Figure 1: Keep it Simple – Simulating an AD4003
Figure 2 zooms in on the conversion of the ramp shown in Figure 1, clearly showing quantization of the ramp signal. The output codes show that transitions between samples happen at the rising edge of the conversion signal (CNV). This fact is critical to the proper design of the AFE (analog front-end), as settling must complete before the start of the next conversion, particularly important when sampling switching or multiplexed signals. This simple circuit also shows when the processor sees the result of a conversion. Note that the settling behavior appears at the input nodes, rather than the output, as the output trace is an approximation of what the digital output would be if reconstructed from digital data [[(see earlier blog)]]. Any error from poor settling appears as an error in the output.
Figure 2: Zooming in on the Quantized Outputs
To see more sampling-related effects, AD4696 16-bit, 16 Channel converter offers a good example. Figure 3 shows how to select the AD4696 using LTspice‘s component dialog.
Figure 3: Choosing the AD4696 in LTspice
Once you have the AD4696 in your scheme, building a simulatable circuit (Figure 4) requires only an input buffer and RC filter.
Figure 4: A Simple Setup for Easy Drive SAR ADCs
Once assembled, the circuit can be set for appropriate sample rate and channel count. AD4696 is a Mux SAR, meaning that the multiplexer is built in. Here, the sample rate is set to 200ksps and two channels, resulting in 100ksps per channel. As noted above, the mux and converter in AD4696 must settle during the sample period, to avoid crosstalk (or “memory”) between channels. Furthermore, the sample and hold circuit injects charge into the inputs, as the sample capacitor must settle to the input value.
These effects inform the design of the RC circuits, which act as charge reservoirs for the sampling capacitor. The RCs must also be designed to keep the input buffer stable, as most amplifiers can drive limited capacitance while remaining stable. The RCs must also allow the input to settle, bringing the RC time constant into the equation, as noted in Figure 4.
Figure 5: Comparison of settling time and charge-injection effects
Figure 5 shows the settling behavior of the circuit. The left side, labeled “No EasyDrive”, shows large signal jumps at each sampling acquisition, resulting in long settling times, and no settling to a high-precision value. This can be addressed by adding additional high-speed buffers and adjusting the RC circuit to optimize settling. The plot on the left is generated with an AD4696-equivalent ADC, but without EasyDrive.
By comparison, the plot on the right, labeled “With EasyDrive”, bounces much less at acquisition, allowing for a shorter settling time and better results at higher sampling rates. EasyDrive is a characteristic of ADI’s ADCs that substantially reduces input charge-injection. This is done in a way that makes the sampling capacitor appear smaller, which is observable as a higher effective input impedance and smaller charge-injection amplitude during acquisition. A design that relies on an ADC with EasyDrive can generally use a lower-bandwidth (and thereby lower-power) amplifier, or possibly no amplifier at all. The resulting precision can be simulated in LTspice for comparison and optimization.
Circuit simulation never can replace bench work, but it can give a designer fast feedback regarding component and feature selection. It is, however, possible to use LTspice to develop a design such that less debug and prototyping are required, saving time and cost.
I hope you have enjoyed this blog series. I encourage the reader to download LTspice and try these examples. Be sure to share your thoughts on the LTspice or the [[ADC/DAC]] EngineerZone forums.