LTspice®︎ Up Your Isolated Gigaspeed Design

If you’ve started cooking for the holidays, then you know that the right spice blend can elevate a dish from good to great. And if the dish you’re cooking happens to be a gigaspeed isolated LVDS design, then you’ve come to the right blog: In this post, we’re going to share the ADI family recipe to help you optimize that design. All you need is a dash of LTspice®.

In the previous blog, we learned what to consider when selecting a power solution for your gigaspeed application. Now that you have chosen a gigaspeed isolation device and associated power solution, it’s time to optimize the design to ensure that it meets your requirements. The LTspice tool from Analog Design Center offers models of many of ADI’s components and a user-friendly interface for this exact purpose.

Let’s take a look at one of those models to see what LTspice  can reveal for us.
 

Optimizing ADN4620 in LTspice 

The ADN4620 model is available in the latest update to LTspice. You will find the model together with a pre-populated test bench that can easily be used to capture the overall performance. Simply search for ADN4620 in the component list.

ADN4620 LTspice test bench

Using this model, you can easily view the overall performance achievable and integrity of high-speed signals through any isolation barrier. Datasheet specifications such as propagation delay and skew are some of the key specifications to review when it comes to high-speed signals.

Propagation delay describes how quickly the signal is transmitted through the LVDS isolator and is especially relevant to the timing and synchronization of signals. Propagation delay errors can lead to system-wide timing errors.

Skew refers to the difference in propagation delay between the two signals in the LVDS differential pair, where the edge of one input deviates from the other. Skew can also be extrapolated from the simulation response.

ADN4620 Propagation delay LTspice simulation 

Although the ADN4620 is an LVDS isolator, it an easily be used with positive referenced emitter coupled logic (PECL) signals as well as current mode logic (CML) signals. Learn more about LVDS, PECL and CML I/O structures.
 

Visualizing Gigaspeed Signal Integrity with LTspice Eye Diagrams

When it comes to high speed signals, jitter is a specification that offers key insights into the quality of a signal. Jitter refers to the apparent movement of the signal’s edge with respect to its ideal position. It can be quantified as errors over time.

Many variables can affect the integrity of the signal, for example different cable lengths, PCB traces, or connections. Thus, it can be helpful to use the eye diagram feature in LTspice to visualize the system’s overall performance. You can review the integrity of gigaspeed signals through the LVDS isolator and easily evaluate any imperfections of the design that could lead to errors.  Check out AN-1177 for more details.

To find the eye diagram feature in LTspice, simply click on the horizontal access of the plot, select the eye diagram button, and select your baud rate.

ADN4620 Eye diagram parameters and readout for default test bench in LTspice
 

Up Next: Gigaspeed Signals for HDMI Applications

Optimizing for gigaspeed signals certainly puts a demand on the design engineer to achieve best performance: as the speed of the data being transmitted increases, so does the importance of signal integrity and overall performance. Optimizing your design in LTspice can provide early performance indicators that could help you save time and cost in the long run.

Come back next time see how the AD462x family are playing their part in protocol isolation across applications such as digital healthcare, industrial automation, and instrumentation. We will take you through the need for isolation in these applications, key design considerations, and some design and layout tips and tricks for isolated HDMI applications.

Read more from the Gigaspeed Isolation series