In last month’s blog post we reviewed the application of Fast Precision DACs in a closed-loop system known as Hardware in the Loop. Since the DAC is driving a physical device, DC precision is required in addition to fast settling time.
DC precision is the main difference between a High-Speed DAC and a Fast Precision DAC. It is often difficult to explain the reason and the implications of this difference, moreover when both types of DACs offer the same resolution and same linearity. It is even disappointing to see that Fast Precision DACs are only scratching the lower limit of High-Speed DACs in terms of update rate. This blog presents and analyzes the differences and similarities of these two types of DACs.
The fact is that Fast Precision DACs and High-Speed DACs are designed for different applications. Figure 1 depicts the way they operate.
Figure 1. Spectral difference between Fast Precision DACs and High-Speed DACs
Let us explore how each type of converter faces the usual design challenges.
Although Fast Precision DACs can be used to generate very clean harmonic signals, in many applications the goal is hitting the right value in one shot. As seen in Figure 2, the signal of a DAC switching between two codes has a fast step followed by a slower convergence to the desired value, known as settling time. To take full advantage of a DAC’s resolution, the peak noise level must be smaller than 1 LSB when the output reaches the steady state.
Figure 2. Settling and convergence of a Fast Precision DAC.
As explained earlier, precision DACs accumulate all the noise from DC up to the bandwidth of the device, which includes 1/f noise and broadband noise. A faster DAC requires more bandwidth to settle faster, which implies more noise, making it harder to keep the LSBs discernible. Therefore, Fast Precision DACs try to minimize the total noise power while High Speed DACs try to keep noise density low in the band of interest, as depicted in Figure 1.
If we assume that peak noise must be smaller than 1 LSB in a Fast Precision DAC, we conclude that there is a limit to how fast it can be for a given resolution. We cannot reduce noise below the thermal noise floor, so this sets a limit to the bandwidth of the signal.
The convergence of the output signal to the final value ultimately follows an exponential approach regardless the output driver has single or conjugate poles. This is an approximation that ignores non-linear effects, but it is useful to get a ballpark idea of the expected performance. Based on this approach, we can estimate the bandwidth required to settle within a given time to a defined accuracy. Results are depicted in Figure 3. For example, if we want the AD3552R to settle to 0.1% accuracy in 100 ns we need the external TIA to have a 3dB bandwidth of 10 MHz. The AD3552R is a dual-channel, 33 MUPS Precision DAC that uses an external TIA for I/V conversion.
Figure 3. Bandwidth required for a 1st order circuit to achieve a given settling time with the specified accuracy.
More bandwidth means more noise, moreover when noise is collected well beyond the 3 dB cutoff frequency. If we impose the requirement that the peak value of this noise must be smaller than 1 LSB, we can calculate how much noise density we can afford for a given settling time and DAC resolution. This is the requirement to make LSBs discernible. The plots in Figure 4 assume that there is no 1/f noise and that the Equivalent Noise Bandwidth (ENBW) corresponds to a first-order circuit. Settling time accuracy is 0.1% on a 5V span.
Figure 4. Maximum noise density for a DAC in order for LSBs to be discernible at a given resolution.
The horizontal line in Figure 4 represents the thermal noise density of a 1 kΩ resistor at 25 °C, that is 4.1 nV/√Hz. Using low ohmic loads with precision DACs is difficult because the voltage span is high and that means a lot of power.
Based on the plots in Figure 4, a 16-bit DAC that settles to 0.1% in 100 ns requires a noise density below 5.6 nV/√Hz to make LSBs discernible on a 5V range. The other way around, if the DAC has a noise density of 10 nV/√Hz it can only afford a settling time of 300 ns in order to preserve the discernibility of the LSBs.
Figure 5 shows an example of a DAC with excessive bandwidth. Changing from code to code is fast enough but the total causes the LSB steps to overlap partially.
Figure 5. In a DAC with excess bandwidth, wideband noise causes the LSB steps to overlap partially.
The scenario is different for High-Speed DACs. These devices are designed to produce signals that are band-limited and periodic within the coherency time. Multi-tone modulations are sensitive to the noise within the bandwidth of each carrier, so the total noise is not relevant. Demodulation takes place during a certain time, so that signal and noise are averaged during this time and therefore the spot value of the signal is not relevant. Modulated signals are usually passband and 1/f noise is not even seen. In summary, High-Speed DACs care more about noise density than about the total noise power.
Another way to look at the speed/precision tradeoff is the time required for the signal to be within 1 LSB for a given bandwidth. The error of an exponential convergence of a DAC with 10 MHz bandwidth is shown in Figure 6.
If a DAC with 10 MHz bandwidth produces a full-scale step, the accuracy after 90 ns is only within 1 LSB8. If we want the signal to be accurate to 1 LSB16, we must wait 180 ns. If we want the DAC to converge faster, we need more bandwidth which implies more noise. At some point it does not pay off to increase the bandwidth because the noise makes the LSBs indiscernible, which results in a reduction of the effective number of bits.
Figure 6. Time required for the signal to be within 1 LSB of given resolution with 10 MHz bandwidth, excluding noise.
High-Speed DACs are usually not required to produce a full-step response, to the point that this data is often not provided in the datasheet. They are mostly used for multi-tone modulations where the signal has a gaussian amplitude distribution and limited spectrum, therefore not requiring full-scale transitions. The high bandwidth allows fast settling in small signal, but the full-scale rise time can be quite large. Table 1 shows a comparison between AD3552R and AD9726, one of the few High-Speed DACs that is quoting these figures. The AD9726 is a 16-bit, 400 MHz wideband DAC.
Small-Signal Settling Time
Rise Time (10%-90%)
Table 1. Rise time and Settling Time Comparison
Precision DACs are intended to drive circuits where the DC value of the signal translates to an absolute level or positioning in the real world. Additionally, we can require the DAC to be fast, but it must remain precise ultimately. This is particularly important in open-loop applications where there is no feedback to perform a correction or no time for such a thing. Being a one-shot application, the DAC must produce first-time-right signals with absolute accuracy.
On the other hand, High-Speed DACs take advantage of the demodulation process where signal is not looked at a spot but over the coherency time. Therefore, the DAC is required to produce a signal with good accuracy, but not necessarily absolute. Noise outside the band of interest is ignored in the demodulation process. The signal may look noisy in time domain but still have reasonable noise levels in frequency domain.
The comparison of these two concepts is presented in Figure 7.
Figure 7. Accuracy requirements for a Fast Precision DAC and a High-Speed DAC.
When dealing with Fast Precision DACs, there is a trade-off between speed and accuracy or otherwise between bandwidth and noise. Settling faster means more bandwidth which conveys more noise that is added to the output signal, eventually making the LSBs indiscernible.
Besides, Fast Precision DACs need to reproduce an accurate signal in a single shot while High-Speed DACs produce signals that are evaluated over a longer period. The former require low total noise and full-scale agility while the second require low noise density and good small-signal bandwidth.