DDS v. PLL nuances (pt I)

As promised in my last post, here is [PART 1 of] a review of some subtleties of the table contrasting DDS/PLL strengths. I know I didn’t [initially] say anything about breaking this up into 2 parts, but after I started writing, I realized it was getting too long for a single entry, so I went back, edited the last post and finished writing this!  

I’ll start with the characteristics I identified as being better suited to a DDS.

Frequency Resolution – There are a few nuances here…

There exists a DDS which runs at 400 MSPS with a 48 bit tuning word (AD9956). This yields a tuning resolution of no worse than 1.42 µHz, yes that’s microHertz.  The resolution of a standard PLL is limited by the depth of the dividers in the loop, and they are a few orders of magnitude worse than this.  I would be remiss however if I didn’t point out that there are fractional-N PLLs (N being the division factor in the feedback divider in the PLL) which close the gap significantly.  There is a downside to using a frac-N PLL: more spurs in the output.  The signals are more jittery. 

Another thing to note is that a standard DDS cannot hit many exact ratios. In the standard DDS frequency equation the denominator is a fixed power of 2.  So, for example, if you have a 200 MHz sample clock, you can hit 50 MHZ exactly (/4), but you cannot hit 40 MHz exactly – you will be off by some tiny bit: if you used the AD9956, you could either be 0.142uHz less than 40 MHz, or 0.568uHz more than 40 MHz. 

Standard PLLs hit these precise ratios quite easily. As such if you need exact ratios, avoid the standard DDS.  BUT that doesn't mean you need to avoid DDS as a whole, if you like the other things about DDS, look to Programmable Modulus!

The Programmable Modulus DDS (which I, affectionately, refer to as p-mod) is a relatively recent innovation in DDS.  A P-MOD DDS allows you to alter the DDS equation so that the denominator is no longer restricted to a power of 2.  No PLL can compete with a P-MOD DDS (AD9913, AD9914, AD9915, AD9164 e.g.) for frequency resolution; I believe that is inherent.  I suspect I will write more about P-MOD in a future entry;  you can also read about it here.

Returning to the 40 MHz example above, the industrious engineer could design a system which used frequency hopping to spend 80% of the time just below 40 MHz and 20% just above 40 MHz, and you would not only end up with a signal that averaged 40 MHz, you would also mimicking the internal workings of a P-MOD.

I promise the rest of these will be shorter!

Frequency Agility

There are ways to introduce varying frequencies in PLLs, but they are not as well controlled, nor are they as repeatable as the digital approach available with DDS.

Frequency hops can be implemented with two parallel PLLs and a switch (They call ‘em ping-pong PLLs – no table, paddles or net required), but you either need one complete PLL for every frequency you might want to hop to, OR you need to allow some settling time if you change the frequency of the bypassed PLL.

You can also sweep frequency with a variable divider in the loop, but it is nowhere near as well-controlled or repeatable as a DDS based sweep

Phase Resolution & Agility

In an analog PLL, any adjustment to phase ends up cycling through the loop, so it’s not a precise, repeatable change like you get with a DDS. Digital PLLs enable some level of phase adjustment capability. 

Amplitude Resolution & Agility

Amplitude is not a parameter that PLLs vary.

Look forward to part II in the not too distant future. Questions may be posed either in the comments, or in the DDS Product Section of ADI’s EngineerZone.