Modern software-defined radio (SDR) and signal analysis systems require efficient capture, processing, and visualization of wideband RF signals to achieve higher accuracy, faster response, and more reliable performance in dynamic communication environments. By optimizing each stage of the DSP chain — from data acquisition to spectral display —engineers can design systems capable of real-time signal monitoring, adaptive filtering, and rapid spectrum characterization, which are essential for modern wireless, radar, and electronic defense applications.
The ADRV9002 from Analog Devices, featuring dual 16-bit ADCs and DACs combined with the Zynq UltraScale+ ZCU102 FPGA platform, provides a powerful framework for implementing real-time digital signal processing pipelines.
In this blog, we build a complete DSP chain that starts with analog signal acquisition via the ADRV9002 transceiver, processes it via an FFT on the ZCU102 FPGA, and visualizes the results on a display or a host GUI. The design uses AXI-based interconnects to achieve a synchronized, deterministic data flow across stages.
Hardware Overview:
The Zynq UltraScale+ ZCU102 combines programmable logic (PL) with high-performance ARM Cortex-A53 processors, offering dedicated AXI interconnects for mixed hardware/software DSP systems.
Key Features:
- 16nm UltraScale+ architecture
- Quad ARM cores + FPGA fabric
- High-bandwidth DDR4 and PCIe interfaces
- default support for AXI interconnects and DMA engines
The ADRV9002 is a highly integrated, dual-channel RF transceiver supporting wideband operation from 30 MHz to 6 GHz.
It includes:
- Dual 16-bit ADCs (sampling up to 61.44 MSPS)
- Dual 16-bit DACs for transmit paths
- Integrated DDC/DUC for baseband conditioning
When connected to ZCU102, the transceiver’s digital interface provides continuous IQ sample streaming directly into the FPGA via LVDS/CMOS interface, where AXI-Stream bridges handle subsequent processing.
DSP Chain Architecture
The DSP pipeline consists of four main stages, connected through AXI interfaces for high-performance modular communication.
1. Data Acquisition (ADRV9002 ADC Interface)
- The analog input is digitized by the 16-bit ADC and serialized through the LVDS link to the FPGA.
- The ZCU102 deserializes and converts this data into AXI-Stream format for processing.
- Each ADC channel can handle sample rates up to 61.44 MSPS, ideal for broadband RF applications.
2. Pre-Processing Stage (DDC or Filtering)
- The baseband signal may be digitally downconverted or filtered using CIC/FIR blocks implemented in FPGA fabric.
- This stage improves the signal-to-noise ratio and isolates the frequency band of interest before spectral analysis.
- AXI-Stream FIFOs ensure stable throughput and decouple clock domains.
3. FFT Core (Spectral Processing)
- The Xilinx FFT IP core receives streaming samples via AXI-Stream input ports.
- Supports parameterizable lengths (e.g., 1024, 2048, or 4096 points).
- Produces real-time frequency-domain data suitable for power spectral density (PSD) estimation or spectrum visualization.
- The output is formatted into magnitude or log-magnitude spectra for display.
4. Data Transfer and Display Interface
- Processed FFT results are streamed to system DDR memory via AXI-DMA.
- The ARM processing subsystem retrieves this data and renders it through a GUI (HDMI or Ethernet).
- Optional Python or Qt-based tools can be used for visualization and analysis.
Figure 1: End-to-end DSP chain using ZCU102 FPGA and ADRV9002 transceiver, demonstrating ADC-to-display signal flow over AXI interconnects.
Implementation Steps on ZCU102
1. Set up JESD204B Interface
- Configure the ADRV9002 IP core in Vivado.
- Connect the RX lane outputs to an AXI-Stream bridge for digital data capture.
2. Design Pre-Processing (DDC or Filter)
- Instantiate a FIR or CIC filter block with AXI-Stream input/output ports.
- Validate latency using the Integrated Logic Analyzer (ILA).
3. Integrate FFT IP Core
- Configure FFT length and data scaling.
- Connect AXI-Stream input from the filter and AXI-Stream output to DMA.
4. AXI-DMA & Memory Mapping
- Map DMA output to DDR for high-throughput burst transactions.
- Use ARM software drivers to manage DMA transfer completion.
5. Visualization and Display
- Develop a simple GUI (Qt/PyQt or Matplotlib) for FFT spectrum visualization.
- Implement communication over UART, Ethernet, or HDMI, depending on system design.
Applications
- Software-Defined Radio (SDR): Real-time spectral monitoring and channel selection.
- Radar Signal Processing: FFT-based range-Doppler estimation.
- Vibration and Acoustic Analysis: Wideband frequency analysis using 16-bit ADC precision.
- Wireless Communication Systems: Baseband and intermediate frequency (IF) processing on FPGA.
- Industrial Sensing: FFT-based data visualization for condition monitoring.
Performance and Flexibility
The integration of the ZCU102 FPGA with the ADRV9002 transceiver showcases how modular DSP architectures can deliver both high performance and design flexibility. Through AXI-based interconnects, data seamlessly flows from acquisition to processing and visualization, while the combination of FPGA-based computation and ARM processors for control ensures an efficient balance between speed, scalability, and adaptability.
This DSP chain can be applied across diverse domains, performing real-time range Doppler analysis in radar systems, spectrum monitoring and modulation analysis in wireless communication, and vibration or acoustic monitoring in industrial environments. These examples highlight how a single FPGA-based framework can be reconfigured to meet the needs of next-generation RF, sensing, and communication systems.
Next Blog Topic: Pulse Compression Using Matched Filter Implementation in FPGA
Read all the blogs in the DSP Building Blocks series.