In the world of software-defined radio (SDR) and high-performance RF systems, properly configuring transceivers is essential for achieving optimal system performance. The ADRV9002 from Analog Devices is a versatile RF transceiver, but to fully harness its potential, developers must be able to create custom profiles tailored to their design requirements.
Transceiver Evaluation Software (TES) simplifies this process, allowing users to generate and export custom profiles for ADRV9002, even without hardware, through Demo Mode. By mastering TES, developers can streamline integration, optimize signal paths, and ensure system compatibility — all of which are critical for building reliable SDR systems on platforms like the ZCU102.
This blog will guide you through generating a custom profile in TES, covering key steps and settings for creating an efficient signal chain configuration
What is TES and Why Use Demo Mode?
TES is a graphical tool designed for:
- Configuration of ADRV9001/ADRV9002 transceivers
- Profile generation and system validation
- FIR filter design and gain planning
- Exporting stream and config files for no-OS or Linux
Note:
To generate a custom profile, you do not need to connect the hardware. TES allows offline configuration through Demo Mode, which is ideal for developers working on initial setups or without board access.
System Requirements
Before you start:
- Install TES for ADRV9002 (latest version from ADI’s website)
- Windows 10/11 PC
- No board is needed for profile generation
- Optional: ZCU102 + ADRV9002 hardware for testing
Step-by-Step: Generating a Custom Profile Using TES
1. Launch TES in Demo Mode
When TES starts, you will see a Platform Selection screen.
Figure 1: TES Launch Window – Select Demo Mode
Choose your configuration:
- Platform: ZCU102 + ADRV9002
- Mode: Demo Mode
- Click Connect
TES will now simulate the hardware, enabling profile generation tools.
2. Open the Profile Configuration Wizard
This opens a guided tool to define your transceiver signal chain and system parameters.
Figure 2: Device Configuration - Main Window
3. Device Configuration
Interface Configuration
Define the number of lanes, serialization rates, and link configuration.
Figure 3: Interface configuration settings
Set Your RF Parameters
Set the following based on your application needs:
- Rx Bandwidth: e.g., 4MHz
- Tx Bandwidth: e.g., 4MHz
- Rx Sampling Rate: e.g., 8 MSPS
Tx Sampling Rate: e.g., 8 MSPS
Figure 4: RF Channel Configuration Tab
4. Board Configuration
Select the external loopback configurations for Tx-channels and SSI reference Clock
Figure 5: Board Configuration Tab
5. Clocks
Device clock configuration for input and output. Default profile come with 38.4MHz clock frequency.
Figure 6: Clock Configuration Tab
6. Clocks
Figure 7 shows the default carrier frequencies. The user can also change the Carrier frequency later using the IIO scope and the command line.
Figure 7: Carrier frequency Configuration Tab
7. Radio
Default configuration of Radio control, Rx/Tx characteristics are shown in Figure 8.
Figure 8: Radio configuration Tab
8. Advanced Features
User can select the multi-chip synchronization mode
Figure 9: Multi-chip synchronization setting tab
9. Rx/Tx Filters
User can provide the custom filter coefficient for the Rx/Tx channel.
Figure 10: Rx Filter configuration tab
10. Export the Profile
Once validated, export the profile via:
File → Export Profile
TES will generate:
- profile.json – for Linux driver
- adi_adrv9001_profile_config.c/.h – for no-OS projects
- .stream file – for boot-time initialization
Figure 11: Profile Export Options
11. Save for Future Use
Keep your custom profile files organized in a dedicated project directory. These will be used in HDL/software integration.
Figure 12: Output Folder with Exported File
Conclusion
Congratulations. If you followed the steps in this blog, you’ve successfully generated a custom profile in TES and settings for an efficient signal chain configuration.
The TES tool is essential for configuring and optimizing the ADRV9002 transceiver. Mastering this tool ensures smoother integration with HDL and software workflows. By working in Demo Mode, engineers can create and test custom RF profiles without immediate hardware access. This speeds up development, especially when targeting platforms like ZCU102. TES also provides precise control over system parameters like bandwidth, sampling rate, and duplexing (FDD/TDD).
In upcoming blogs, DSP Building Blocks series, we’ll apply these profiles in real FPGA systems. Stay tuned to level up your RF and FPGA development.