How to Build the Xilinx Default HDL Project for ZCU102 on Windows

There are many, many hardware and software tools to choose from when designing field programmable gate arrays (FPGAs). For creating and testing custom designs, the Xilinx hardware description language (HDL) projects are commonly used in tandem with the ZCU102 hardware/software design platform. ZCU102 is favored for its high-speed, high-performance capabilities and because it offers a single platform for integrating hardware, software, IP, and reference designs.

This blog provides a step-by-step guide on how to build the default Xilinx HDL project for the ZCU102 on a Windows system using the Cygwin application. Cygwin is essential, as it creates a Unix-like environment on Windows, enabling the use of various Linux tools.

To get started, ensure you have the following set up:

• AMD (Xilinx) Vivado (any version, ex. 2021.1)
• AMD (Xilinx) Vitis (version matching Vivado)
• Cygwin (a Linux-like environment for Windows), along with necessary libraries
• Git, make, gcc, and g++ installed through Cygwin
   

Step-by-Step Guide: Building the Xilinx Default HDL Project for ZCU102 on Windows

Let’s dive into the steps to build the HDL project.
 

Step 1: Install Cygwin

First, download and install Cygwin. During installation, ensure you select the following packages to install. These libraries are critical for running build commands and handling source control within Cygwin.

• git
• make
• gcc
• g++

Step 2: Set Up Your Project Directory

Create a folder on your computer where you want to download resource files and perform the build. Example: C:\Projects\ZCU102_hdl

Step 3: Export Vivado and Vitis Directories

With Cygwin installed, the next step is to set the environment paths for Vivado and Vitis. This step ensures that all necessary tools are accessible in the Cygwin environment. Open Cygwin and export the paths:

export PATH=$PATH:/cygdrive/C/Xilinx/2021.1/Vivado/2021.1/bin
export PATH=$PATH:/cygdrive/C/Xilinx/2021.1/Vitis/2021.1/bin

Adjust the paths above to reflect the exact installation paths for Vivado and Vitis on your system. This example uses the default paths assuming Vivado and Vitis are installed under C:\Xilinx.
 

Step 4: Verify Exported Paths

This step helps confirm that Cygwin correctly recognizes both Vivado and Vitis. If it does, you should see the version details displayed. Once you’ve set the paths, verify they are correctly exported by typing:

which vivado

which vitis

Step 5: Download the HDL Files

With the environment ready, you can now download the HDL files from Analog Devices’ GitHub repository. In your project directory, clone the HDL repository:

git clone https://github.com/analogdevicesinc/hdl

Step 6: Prepare and Build the HDL Project

Now that you have the repository cloned, it’s time to configure and build the project for the ZCU102.

1. Navigate to the hdl directory: cd hdl
2. Check the Git repository status: git status
3. Switch to the appropriate branch for your version of Vivado, ex. 2021.1: git checkout hdl_2021_r2
4. Fetch the latest updates: git fetch origin
5. Rebase to make sure you have the latest files: git rebase origin/hdl_2021_r2
6. List the contents to ensure everything is in place: ls
7. Move to the ZCU102 project directory: cd projects/adrv9001/zed
8. Run the make command to build the HDL project: make CMOS_LVDS_N=0

This command triggers the build process, which may take a few minutes; the system will be compiling the HDL sources and generating the required bitstream file for the ZCU102. For different settings, use CMOS_LVDS_N=0 for LVDS or CMOS_LVDS_N=1 for CMOS.

Step 7: Open the Project in Vivado

Once the make process completes, you can open the project in Vivado.

1. Open Vivado, and from the main menu, choose File > Open Project.
2. Navigate to the project directory where the .xpr file is located and open it.

Dive Into Your Next FPGA Project with Windows Cygwin

Well done! Your ZCU102's default Xilinx HDL project is now constructed and prepared in Vivado for either straight deployment or additional customization. As you can see, it is not difficult to build the Xilinx default HDL project for ZCU102 in a Windows Cygwin environment. This method allows a great scope of further customization and easy incorporation with other tools in the scope of the FPGA workflow. Thanks to the capabilities of Vivado and Vitis and ADI’s support for these tools, this blog should help you dive right into your next FPGA project.

Coming up next: In the upcoming blog of this series, I will cover how to generate and integrate No-OS application files specifically for the ADRV9002 with the default HDL project. This will include a detailed explanation on linking the No-OS application to the HDL design to create a comprehensive FPGA-based system.

Read more: The complete "Technology for eXtreme Optimization and Real-Time" blog series