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Quick Guide: Key Points on Setting Up AXI DMA for Streaming Data

Muhammad Ijaz
1 minute read time.

In the FPGA-based digital signal processing (DSP) world, system performance is often constrained by the speed and efficiency of data movement between memory and custom logic blocks. High-speed applications like modern radar receivers, data acquisition systems, and wireless basebands require continuous data streaming at gigabytes per second. Relying on a CPU for this task is inefficient and unreliable. TL;DR the how -to guide "RTL Design and Verification of AXI DMA for Streaming Data". This is a summary of the key points on configuring AXI Direct Memory Access (DMA) in Vivado for both Memory Mapped to Stream (MM2S) and Stream to Memory Mapped (S2MM) modes, helping you achieve high-performance data movement with minimal latency and maximum efficiency. 

Importance of Efficient Data Movement:

  • Critical for high-performance FPGA-based DSP systems.
  • Reducing CPU intervention and latency to a minimum.

Key Features of AXI DMA Modes:


MM2S (Memory Mapped to Stream):
Sends data from memory to a stream.

  • Utilizes a single AXI4 Main interface for read operations.
  • Employs an AXI4-Stream interface for output.


S2MM (Stream to Memory Mapped):

  • Captures data from a stream and writes it back to memory.
  • Utilizes a Subordinate AXI4 interface for writing.
  • Utilizes AXI4-Stream interface for input.

 

System Architecture:


Zynq Processing System (PS):

  • Incorporating the processor and DDR memory controller.

AXI DMA (PL):

  • Manages data transfer between DDR memory and AXI streaming interfaces.

AXI4-Stream Data FIFO (PL):

  • Buffers data between the MM2S and S2MM DMA streams.

AXI-Lite Interface:

  • Used for processor to DMAC configuration and status.


AXI4 Memory-Mapped Interfaces:

  • Manages data movement to and from memory.


AXI4-Stream Interfaces:

  • Enable high-speed data streams without buffering or addressing.

 

Loopback Design Example:

  • Illustrates the use of AXI DMA and a FIFO on the Zedboard.
  • The AXI DMA engine handles data transfer between DDR and the FPGA fabric.
  • The FIFO serves as a buffer to interconnect the MM2S and S2MM paths.
  • Ideal for continuous, high-speed data streaming applications, like radar and communications systems.
  • Minimizing CPU intervention and latency.

 

To read the full blog post RTL Design and Verification of AXI DMA for Streaming Data how-to guide, click here.

Tags: DSP Building Blocks FPGA DSP Design wireless communications wireless communication