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ADEMA127 timing requirements

thiagopradop on Jun 23, 2026

Category: Datasheet/Specs

Product Number: ADEMA127

We are designing a system with two ADCs (ADEMA127 and ADEMA124) that will be individually addressed, sharing the same clock source and configurations.

Our clock source is 5.12 MHz, which will result in a 10 ksps final sample rate.

We could not find the following two timing specifications in the ADEMA124/127 datasheet. We want to use the RESET pin to reset the ADCs before configuring them, and after setup, we will send the sync spi command + CS sync pulse.

1. How long must the RESET pin be held LOW to ensure a valid hardware reset of the ADC?

2. How long must the CS pin be held low for triggering the sync?

Any guidance would be appreciated.

Analog to Digital Converters (ADCs) Datasheet/Specs ADEMA127 reset timing synchronization Show More

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jnaso

on Jun 25, 2026 3:10 PM
0
Hi,

The RESETb pin needs to be held low >1.5ms to guarantee a reset is triggered.

The CSb has a much narrower glitch filter... The typical width is 1.5ns. I would recommend following the tDAV specs and make sure the pulse width is >20ns.

Regards,

Jason
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thiagopradop on Jun 25, 2026 3:56 PM in reply to jnaso
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Thanks. Is the reset time related to the clock value? If 1.5 ms works for 16.384 MHz, should I use a greater time for 5.12 MHz (something like 5 ms to keep it proportional)?
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thiagopradop on Jun 25, 2026 3:56 PM in reply to jnaso
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Thanks. Is the reset time related to the clock value? If 1.5 ms works for 16.384 MHz, should I use a greater time for 5.12 MHz (something like 5 ms to keep it proportional)?
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ADEMA127 timing requirements

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