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Fast RMS settling time behaviour on Pulse modulated waveform

Thread Summary

The user faced issues measuring RMS current in a three-phase system with short conduction cycles using the ADE9000. The solution involved syncing the firmware with the TRIAC firing of the PWM controller to capture RMS readings during the last half of a conducting window, achieving stable readings within the required 60ms settling time. The high-pass filter was enabled, and the integrator was disabled to ensure accurate measurements.
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Category: Datasheet/Specs
Product Number: ADE9000

Hi! 

I'm having a tough problem here when trying to measure RMS current for three phase systems with short conduction cycles.

I'm trying to measure IRMS on a low frequency PWM controller and sometimes the conduction cycle can get very low reaching even 2-3 line cycles.

On this thread ->  Fast RMS over one line Cycle <-  the proposed method was to use the Ipeak register synchronized with the Zero crossing which worked flawlessly for single phase systems. Problem is that on three phase systems the IPEAK register only holds the maximum value out of the three phases. So monitoring any type of unbalance is not possible. What I triyed to do was to cycle between each phase enabling the peak detection only for the desired phase every time. It works, i can effectively get the peak for each phase and even if any unbalance happens i can detect it. But this breaks my surge protection feature as I am not able to monitor all three phases at the same time.

Only solution I was able to find was using fast RMS and having my system only measure currents after a given conduction window.I'd be able to measure every phase, detect any unbalance and still be able to detect and treat surges on a single line cycle. But now 'm not able to reach the settling times shown by the datasheet  (UG-1098) .

I was able to confirm the 260mS by just keeping the default settings but was not able to measure anything when reducing the time to this 60mS. What register configurations are necessary to achieve this 60mS settling time?

I tried both RMS_SRC_SEL = 1 and 0 on Cofig0. also made sure the HPFDIS and INTEN were at 0 (high pass filter not disabled(ON)  and Integrator not enabled(off)). LPF2 comes enabled by defautl at reset so I didn't tampered with it.

Also, just for more context, I'm running the tests with a conduction cycle of 120mS to provide at least one full conduction window (which i think should compensate for the random start of the capture).

For instance for a 60Hz signal:

60ms(settling time) +16,67mS(one cycle) +8,33mS(half cycle for the update meas)+35mS(extra time) = 120mS(total time)