ADE9000 – Current channels drifting 853–1127 ppm/°C while voltage channels remain stable

I am a little confused. The datasheet for the current sensor states 0.3% of reading https://www.hioki.com/us-en/products/current-probes/ac-current/id_5902

 +/-3000ppm accuracy

Are you sure the equipment you are using is good enough to support your claim. 

Dave

Also want to note the ref drift is 25ppm. 

The individual measurements are stated in %error. At high amplitudes approaching full-scale is the best performance with increased SNR.

This is a system so your ct and burden is also included in the drift.

are you using a single ended burden?  how are you grounding your current channels? 

Dave

Thanks Dave for your interest. The burden resistors are self contained in the HIOKI CTs and far from the ADE9000, I'm cycling just the ADE9000 dice with cold or hot air, the 9000's front end is exacly the one used on de EVAL-ADE9000, two IK resistors, two 22nF to ground at the Clamp connector and two 22nF to ground at the 9000 ADC current pins.

Regarding the HIOKI 9660 accuracy: only the ADE9000 die is being thermally cycled with cold and hot air. The HIOKI sensors are at ambient temperature, 50 cm away, and completely outside the thermal loop. The voltage channels, under identical conditions, show no drift at all. This clean asymmetry is consistent across two independent ADE9000 units, which is why we believe the drift originates inside the current channel datapath of the chip itself.

The ADC are identical for Voltage and current. Can you show how the current sensor is connected to the current channel ADC from sensor to ADC inputs. Are you grounding one side of the current sensor? Have you measured the ADC inputs to see if it is drifting over temp?

in technical Ref manual UG-1098 (Rev.A) pg 5   The center tapped burden fixes the common mode to 0.

Another option is single ended. This requires one leg to be grounded to fix the common mode to 0.

Dave

Thanks DAVE, the HIOKI burden resistor is inside the clamp, so there is no way to build a center tapped burden pair, except if I install two, let's say 10K resistors from each pin to gnd. I'll do that.

Dave, you nailed it. The floating common mode was the root cause all along.

I ran a quick experiment: added 10kΩ resistors from each HIOKI CT output pin to AGND on Phase A only, leaving Phase B and C unchanged. The results are conclusive — over a temperature sweep from −3°C to 29°C, Phase A current remained rock solid at ~23.00 A with less than 0.02 A variation, while Phase B and C drifted by approximately 0.7 A and 0.6 A respectively over the same range.

Two ADE9000 units, weeks of investigation, and the fix was two resistors. Thank you for pointing us in the right direction — we would not have found it without your guidance.

Dave, the fix worked perfectly. Here are the results:

Before (floating common mode):

• Current channels drift: 853–1127 ppm/°C
• Voltage channels: stable

After (6 × 10kΩ resistors from each CT output pin to AGND):

• All three current channels: ~18.4 ppm/°C
• Full temperature sweep from 15°C to 30°C
• All three phases consistent and stable

The measured system drift of 18.4 ppm/°C is well within the ±25 ppm/°C maximum specified in the datasheet, and this figure includes the entire signal chain — ADE9000, voltage dividers, and current sensors.

The root cause was exactly what you pointed out: the HIOKI 9660 CT outputs are floating, with no common mode reference to AGND. Without the center tap, the PGA input bias current interacted with temperature, causing the drift exclusively on the current channels while the voltage channels remained stable.

Two weeks of investigation, two ADE9000 units tested, and the fix was six resistors. Thank you for your guidance — we would not have found it without your expertise.