Hello,
I'm currently developing a system using eight ADE9430 ICs for high-accuracy, polyphase energy and power quality monitoring. A key requirement for my application is to have all devices start sampling their inputs simultaneously, or with minimal time skew, to ensure temporal alignment across all channels.
Given that the ADE9430 doesn’t provide dedicated synchronization signals like SYNC_IN or SYNC_OUT, I would appreciate guidance on how to best synchronize multiple ICs.
Some specific considerations:
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All ADE9430 devices will share a common external clock source on their CLKIN pins to ensure uniform timing at the hardware level.
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I’m considering using a common hardware reset signal to simultaneously reset all chips, but I’m unsure whether this alone ensures deterministic sampling alignment once the devices resume operation.
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Communication is handled over SPI. I’m curious if it’s feasible to issue a broadcast command (e.g., simultaneous writes via shared MOSI and SS lines) that could be used to align internal sampling logic across the chips. Is there a particular register write or event trigger that could act as a software-based "start" signal?
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I would also like to understand whether there are any recommended practices for minimizing timing skew in systems with multiple ADE9430s, such as layout considerations, register initialization sequences, or timing alignment via the data-ready or interrupt signals.
If you’ve worked with multi-ADE9430 setups or know of any techniques to achieve tight synchronization, I’d greatly appreciate your insight.
Thank you very much for your time and assistance.
