Hello ,
"I am currently working with the ADE7953 metering IC. I have reviewed the datasheet, but I have not found any guidance on how to convert the raw reading from the IRMSA_32 register into an actual value." please hep me .
ADE7953
Production
The ADE7953 is a high accuracy electrical energy measurement
IC intended for single phase applications. It measures line voltage
and current and calculates...
Datasheet
ADE7953 on Analog.com
Hello ,
"I am currently working with the ADE7953 metering IC. I have reviewed the datasheet, but I have not found any guidance on how to convert the raw reading from the IRMSA_32 register into an actual value." please hep me .
Have you looked at the calibration document? AN-1118 (Rev. B) (analog.com)
Dave
yes , but not get ...
quick and dirty.
supply test current rms/lsb = test current / codes in rms register.
This requires the test current to be accurate. More accurate than your accuracy requirement.
I have attached some example code using arduino and a bluepill stm32f103. This code works thru calibration doc with known current and voltage.
ade7953_bluepill_spi_cal_5_17p5_23.TXT
Dave
//Table 13 8-Bit Registers Address Register Name // R/W Default Type Register Description #define SAGCYC 0x000 // R/W 0x00 Unsigned Sag line cycles #define DISNOLOAD 0x001 // R/W 0x00 Unsigned No-load detection disable (see Table 16) #define LCYCMODE 0x004 // R/W 0x40 Unsigned Line cycle accumulation mode configuration (see Table 17) #define PGA_V 0x007 // R/W 0x00 Unsigned Voltage channel gain configuration (Bits[2:0]) #define PGA_IA 0x008 // R/W 0x00 Unsigned Current Channel A gain configuration (Bits[2:0]) #define PGA_IB 0x009 // R/W 0x00 Unsigned Current Channel B gain configuration (Bits[2:0]) #define WRITE_PROTECT 0x040 // R/W 0x00 Unsigned Write protection bits (Bits[2:0]) #define LAST_OP 0x0FD // R 0x00 Unsigned Contains the type (read or write) of the last successful communication (0x35 = read; 0xCA = write) #define LAST_RWDATA 0x0FF // R 0x00 Unsigned Contains the data from the last successful 8-bit register communication #define Version 0x702 // R N/A Unsigned Contains the silicon version number #define EX_REF 0x800 // R/W 0x00 Unsigned Reference input configuration: set to 0 for internal;set to 1 for external //Table 14 16-Bit Registers Address Register Name // R/W Default Type Register Description #define ZXTOUT 0x100 // R/W 0xFFFF Unsigned Zero-crossing timeout #define LINECYC 0x101 // R/W 0x0000 Unsigned Number of half line cycles for line cycle energy accumulation mode #define CONFIG 0x102 // R/W 0x8004 Unsigned Configuration register (see Table 18) #define CF1DEN 0x103 // R/W 0x003F Unsigned CF1 frequency divider denominator. When modifying this "register,two" sequential write operations must be performed to ensure that the write is successful. #define CF2DEN 0x104 // R/W 0x003F Unsigned CF2 frequency divider denominator. When modifying this "register,two" sequential write operations must be performed to ensure that the write is successful. #define CFMODE 0x107 // R/W 0x0300 Unsigned CF output selection (see Table 19) #define PHCALA 0x108 // R/W 0x0000 Signed Phase calibration register (Current Channel A). This register is in sign magnitude format. #define PHCALB 0x109 // R/W 0x0000 Signed Phase calibration register (Current Channel B). This register is in sign magnitude format. #define PFA 0x10A // R 0x0000 Signed Power factor (Current Channel A) #define PFB 0x10B // R 0x0000 Signed Power factor (Current Channel B) #define ANGLE_A 0x10C // R 0x0000 Signed Angle between the voltage input and the Current Channel A input #define ANGLE_B 0x10D // R 0x0000 Signed Angle between the voltage input and the Current Channel B input #define Period 0x10E // R 0x0000 Unsigned Period register #define ALT_OUTPUT 0x110 // R/W 0x0000 Unsigned Alternative output functions (see Table 20) #define LAST_ADD 0x1FE // R 0x0000 Unsigned Contains the address of the last successful communication #define LAST_RWDATA 0x1FF // R 0x0000 Unsigned Contains the data from the last successful 16-bit register communication #define Reserved 0x120 // R/W 0x0000 Unsigned This register should be set to 30h to meet the performance specified in Table 1 To modify this "register," it must be unlocked by setting Register Address 0xFE to 0xAD immediately prior. //24-Bit 32-Bit Registers "," r/w "," default "," description #define SAGLVL_24 0x200 #define SAGLVL_32 0x300 //R/W 0x000000 Unsigned Sag voltage level #define ACCMODE_24 0x201 #define ACCMODE_32 0x301 //R/W 0x000000 Unsigned Accumulation mode (see Table 21) #define AP_NOLOAD_24 0x203 #define AP_NOLOAD_32 0x303 //R/W 0x00E419 Unsigned Active power no-load level #define VAR_NOLOAD_24 0x204 #define VAR_NOLOAD_32 0x304 //R/W 0x00E419 Unsigned Reactive power no-load level #define VA_NOLOAD_24 0x205 #define VA_NOLOAD_32 0x305 //R/W 0x000000 Unsigned Apparent power no-load level #define AVA_24 0x210 #define AVA_32 0x310 // R 0x000000 Signed Instantaneous apparent power (Current Channel A) #define BVA_24 0x211 #define BVA_32 0x311 // R 0x000000 Signed Instantaneous apparent power (Current Channel B) #define AWATT_24 0x212 #define AWATT_32 0x312 // R 0x000000 Signed Instantaneous active power (Current Channel A) #define BWATT_24 0x213 #define BWATT_32 0x313 // R 0x000000 Signed Instantaneous active power (Current Channel B) #define AVAR_24 0x214 #define AVAR_32 0x314 // R 0x000000 Signed Instantaneous reactive power (Current Channel A) #define BVAR_24 0x215 #define BVAR_32 0x315 // R 0x000000 Signed Instantaneous reactive power (Current Channel B) #define IA_24 0x216 #define IA_32 0x316 // R 0x000000 Signed Instantaneous current (Current Channel A) #define IB_24 0x217 #define IB_32 0x317 // R 0x000000 Signed Instantaneous current (Current Channel B) #define V_24 0x218 #define V_32 0x318 // R 0x000000 Signed Instantaneous voltage (voltage channel) #define IRMSA_24 0x21A #define IRMSA_32 0x31A // R 0x000000 Unsigned IRMS register (Current Channel A) #define IRMSB_24 0x21B #define IRMSB_32 0x31B // R 0x000000 Unsigned IRMS register (Current Channel B) #define VRMS_24 0x21C #define VRMS_32 0x31C // R 0x000000 Unsigned VRMS register #define AENERGYA_24 0x21E #define AENERGYA_32 0x31E // R 0x000000 Signed Active energy (Current Channel A) #define AENERGYB_24 0x21F #define AENERGYB_32 0x31F // R 0x000000 Signed Active energy (Current Channel B) #define RENERGYA_24 0x220 #define RENERGYA_32 0x320 // R 0x000000 Signed Reactive energy (Current Channel A) #define RENERGYB_24 0x221 #define RENERGYB_32 0x321 // R 0x000000 Signed Reactive energy (Current Channel B) #define APENERGYA_24 0x222 #define APENERGYA_32 0x322 // R 0x000000 Signed Apparent energy (Current Channel A) #define APENERGYB_24 0x223 #define APENERGYB_32 0x323 // R 0x000000 Signed Apparent energy (Current Channel B) #define OVLVL_24 0x224 #define OVLVL_32 0x324 // R/W 0xFFFFFF Unsigned Overvoltage level #define OILVL_24 0x225 #define OILVL_32 0x325 // R/W 0xFFFFFF Unsigned Overcurrent level #define VPEAK_24 0x226 #define VPEAK_32 0x326 // R 0x000000 Unsigned Voltage channel peak #define RSTVPEAK_24 0x227 #define RSTVPEAK_32 0x327 // R 0x000000 Unsigned Read voltage peak with reset #define IAPEAK_24 0x228 #define IAPEAK_32 0x328 // R 0x000000 Unsigned Current Channel A peak #define RSTIAPEAK_24 0x229 #define RSTIAPEAK_32 0x329 // R 0x000000 Unsigned Read Current Channel A peak with reset #define IBPEAK_24 0x22A #define IBPEAK_32 0x32A // R 0x000000 Unsigned Current Channel B peak #define RSTIBPEAK_24 0x22B #define RSTIBPEAK_32 0x32B // R 0x000000 Unsigned Read Current Channel B peak with reset #define IRQENA_24 0x22C #define IRQENA_32 0x32C // R/W 0x100000 Unsigned Interrupt enable (Current Channel "A," see Table 22) #define IRQSTATA_24 0x22D #define IRQSTATA_32 0x32D // R 0x000000 Unsigned Interrupt status (Current Channel "A," see Table 23) #define RSTIRQSTATA_24 0x22E #define RSTIRQSTATA_32 0x32E // R 0x000000 Unsigned Reset interrupt status (Current Channel A) #define IRQENB_24 0x22F #define IRQENB_32 0x32F // R/W 0x000000 Unsigned Interrupt enable (Current Channel "B," see Table 24) #define IRQSTATB_24 0x230 #define IRQSTATB_32 0x330 // R 0x000000 Unsigned Interrupt status (Current Channel "B," see Table 25) #define RSTIRQSTATB_24 0x231 #define RSTIRQSTATB_32 0x331 // R 0x000000 Unsigned Reset interrupt status (Current Channel B) N/A 0x37F CRC // R 0xFFFFFFFF Unsigned Checksum #define AIGAIN_24 0x280 #define AIGAIN_32 0x380 // R/W 0x400000 Unsigned Current channel gain (Current Channel A) #define AVGAIN_24 0x281 #define AVGAIN_32 0x381 // R/W 0x400000 Unsigned Voltage channel gain #define AWGAIN_24 0x282 #define AWGAIN_32 0x382 // R/W 0x400000 Unsigned Active power gain (Current Channel A) #define AVARGAIN_24 0x283 #define AVARGAIN_32 0x383 // R/W 0x400000 Unsigned Reactive power gain (Current Channel A) #define AVAGAIN_24 0x284 #define AVAGAIN_32 0x384 // R/W 0x400000 Unsigned Apparent power gain (Current Channel A) //0x285 Reserved_24 //0x385 Reserved_32 // R/W 0x000000 Signed This register should not be modified. #define AIRMSOS_24 0x286 #define AIRMSOS_32 0x386 // R/W 0x000000 Signed IRMS offset (Current Channel A) //0x287 Reserved_24 //0x387 Reserved_32 // R/W 0x000000 Signed This register should not be modified. #define VRMSOS_24 0x288 #define VRMSOS_32 0x388 // R/W 0x000000 Signed VRMS offset #define AWATTOS_24 0x289 #define AWATTOS_32 0x389 // R/W 0x000000 Signed Active power offset correction (Current Channel A) #define AVAROS_24 0x28A #define AVAROS_32 0x38A // R/W 0x000000 Signed Reactive power offset correction (Current Channel A) #define AVAOS_24 0x28B #define AVAOS_32 0x38B // R/W 0x000000 Signed Apparent power offset correction (Current Channel A) //24-Bit 32-Bit Register Name // R/W Default Type Register Description #define BIGAIN_24 0x28C #define BIGAIN_32 0x38C // R/W 0x400000 Unsigned Current channel gain (Current Channel B) #define BVGAIN_24 0x28D #define BVGAIN_32 0x38D // R/W 0x400000 Unsigned This register should not be modified. #define BWGAIN_24 0x28E #define BWGAIN_32 0x38E // R/W 0x400000 Unsigned Active power gain (Current Channel B) #define BVARGAIN_24 0x28F #define BVARGAIN_32 0x38F // R/W 0x400000 Unsigned Reactive power gain (Current Channel B) #define BVAGAIN_24 0x290 #define BVAGAIN_32 0x390 // R/W 0x400000 Unsigned Apparent power gain (Current Channel B) //0x291 Reserved_24 //0x391 Reserved_32 // R/W 0x000000 Signed This register should not be modified. #define BIRMSOS_24 0x292 #define BIRMSOS_32 0x392 // R/W 0x000000 Signed IRMS offset (Current Channel B) //0x293 Reserved_24 //0x393 Reserved_32 // R/W 0x000000 Unsigned This register should not be modified. //0x294 Reserved_24 //0x394 Reserved_32 // R/W 0x000000 Unsigned This register should not be modified. #define BWATTOS_24 0x295 #define BWATTOS_32 0x395 // R/W 0x000000 Signed Active power offset correction (Current Channel B) #define BVAROS_24 0x296 #define BVAROS_32 0x396 // R/W 0x000000 Signed Reactive power offset correction (Current Channel B) #define BVAOS_24 0x297 #define BVAOS_24 0x397 // R/W 0x000000 Signed Apparent power offset correction (Current Channel B) #define LAST_RWDATA_24 0x2FF #define LAST_RWDATA_32 0x3FF // R 0x000000 Unsigned Contains the data from the last successful 24-bit/32-bit register communication
thank you sir for giving your value able time .
Now i am getting reading . I am using CT at channel A and Shunt of 300micor ohm for channel b . Channel A is working fine . But channel B is giving non linear reading of current . Please check schematic . Is there any correction required .