ADE78xx layout

I am comparing different EVAL-kit gerbers.
- On the last one (UG-545 Rev. 0) the second layer (GND) is split under the current measurement routings, but not under the voltage inputs.
- The bottom GND layer is split on both current and voltage islands. There is a trace across to connect Neutral to the other ones too.
- The clearances on the gerber between voltage inputs and GND seem to small to satisfy a picky approval agent.
- Guard rings are encircling the whole input lines, not just the high impedance regions. IMO it is good for isolating adjacent low voltage traces, but the high voltage parts could affect their own 1000:1 segments much more than the adjacent low impedance line inputs.

  • The evaluation board is not designed to be copied for a meter design it is used for bench evaluation and characterization in house. The goal is best ADC performance and it it large to accommodate a temperature head for Characterization over temp. A bigger issue with that board is a single 1 Meg resistor on the voltage channel. The footprint of this resistor has more parasitic capacitance than a 3 resistor string that equals 1M. this causes coupling around the 1 Meg resistor and impacts performance over freq and voltage. use multiple resistors for increases creepage and lower parasitic capacitance. 

    layout guidelines on the datasheet pg70 highlight the critical component placements around the ade78xx

    https://www.analog.com/media/en/technical-documentation/data-sheets/ade7854a_7858a_7868a_7878a.pdf

    Dave

  • I've found that one in the data sheet (page 70) but it is only on quartz and decoupling caps. They are OK. I am more concerned about the measurement input layout like guard rings. I already implemented the 1M as 3x333k resistors, they are used in another Analog pcb. However I didn't know about the parasitic capacitance of 1206 being such an issue!
    If you have another suggestions I'd appreciate them!
    Akos

  • Guard rings are not required in a metering application. Keep the current channel traces next to each other for common mode rejection. The anti alias cap should be close to the ADE78xx the resistor can be close to the ct input  or where ever you can fit it. The placement of the caps is most important and should be close to the ADE78xx. 

    try to tied the current channel anti alias caps tot eh same via if possible, the goal is the same ground point for common mode performance.  on page 70 you will also see the recommended ground connection using the pad. AGND and DGND should be tied tot he same gnd using the pad. 

    Dave