ADE9153A PCB Layout Issue

Hi,

I made a PCB board based on the EV-ADE9153ASHIELDZ. The voltage channel works fine. However the I-channel does not work as expected.

The software was tested on EV-ADE9153ASHIELDZ and works fine on both I and V channel. Since the I and V channel of my board is basically copied from the shield board, we can eliminate software bugs or wrong register settings at the moment.

On my board, after calibration, the calculated MS_ACAL_AICC value was around 40,000. This value was far away from the expecting value. (around 838 for 1mohm shunt with 16x gain).

I swapped the IC and the shunt between my board and the shield board. The shield board works fine and our board still have the same problem. So the IC and the shunt are not the root cause. I also replaced the R and C around the I channel. No improvement whatsoever.

I guess the problem should be related to the PCB layout. But I don't know which part went wrong.

Below is part of our PCB. The trace width of the IAMS is 1.5mm as recommended. It is actually wider than that on the shield board.

I would be appreciated if anyone can give me some advise.

By the way, does PCB material or copper thickness matter?

Thanks for help

Zack

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  • Hi Zack,

    From your description, it sounds like you're having a massive error in the MS_ACAL_AICC result and that would point me to believe that there should be some large error in the layout or schematic which we should be able to track down.

    First off, along with the MS_ACAL_AICC value, what MS_ACAL_AICERT value are you reading on each board?

    Second, any chance you could share the layout in some way where I can see the layers, for example screenshots of the gerbers with the shunt and ADE9153A included? I would like to be able to see each layer and all the connections. In addition, the schematic would be helpful as well. The picture above helps but doesn't quite give enough information.

    In the picture above, the only thing that standouts to me is that the ground plane for the return of the mSure signal does narrow out on the top layer but that shouldn't give you such a large error. If I could see the partial or full layout/schematic I mentioned above that would be a big help.

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  • Hi Zack,

    From your description, it sounds like you're having a massive error in the MS_ACAL_AICC result and that would point me to believe that there should be some large error in the layout or schematic which we should be able to track down.

    First off, along with the MS_ACAL_AICC value, what MS_ACAL_AICERT value are you reading on each board?

    Second, any chance you could share the layout in some way where I can see the layers, for example screenshots of the gerbers with the shunt and ADE9153A included? I would like to be able to see each layer and all the connections. In addition, the schematic would be helpful as well. The picture above helps but doesn't quite give enough information.

    In the picture above, the only thing that standouts to me is that the ground plane for the return of the mSure signal does narrow out on the top layer but that shouldn't give you such a large error. If I could see the partial or full layout/schematic I mentioned above that would be a big help.

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