To Update from ADE7816 to ADE9000

Previously I am using ADE7816 energy metering ic for the single phase energy monitoring purpose, I use 6000 line cycles as count in the LINECYC register to configure it for 1 min.

Now, I need to use ADE9000 ic for Three phase energy monitoring purpose. please suggest me Registers to be used and count value to write in the Registers for the period of 1 min.

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  • Hi Mr. Katikam,

    You need to configure WATTACC/VARACC in the ACCMODE register to select accumulation modes.

    Take not of the EP_CFG register and configure NOLOAD,  EGY_TMR_MODE for line cycle accumulation. Configure the number of half line cycles in EGY_TIME.For EGY TIME

    You can use half line cycles or the internal update rate of the chip (which depends on you choice in the EP_CFG register in the EGY_TMR_MODE.

    I will give an example here for 1 minute using the half line cycles of the chip and the internal rate of the chip.

    time in seconds = (EGY_TIME + 1)/ZX Rate

    Example, 60 seconds half line accumulations for a 50 Hz fundamental signal.

    ZX rate = zero crossing rate or twice fundamental frequency

    for ZX Rate of 100 Hz and 60 seconds time, EGY_TIME is 0d5999

    You can use this formula when your accumulation is updated using the internal rate of the chip:

    Please refer to the page 50 of this document for more details and a complete guide that includes reset, INTEN bits, Fundamental frequency, zero crossing, and other status configurations.

    https://www.analog.com/media/en/technical-documentation/user-guides/ADE9000-UG-1098.pdf

    Hope this helps.

    Regards,

    Aaron

Reply
  • Hi Mr. Katikam,

    You need to configure WATTACC/VARACC in the ACCMODE register to select accumulation modes.

    Take not of the EP_CFG register and configure NOLOAD,  EGY_TMR_MODE for line cycle accumulation. Configure the number of half line cycles in EGY_TIME.For EGY TIME

    You can use half line cycles or the internal update rate of the chip (which depends on you choice in the EP_CFG register in the EGY_TMR_MODE.

    I will give an example here for 1 minute using the half line cycles of the chip and the internal rate of the chip.

    time in seconds = (EGY_TIME + 1)/ZX Rate

    Example, 60 seconds half line accumulations for a 50 Hz fundamental signal.

    ZX rate = zero crossing rate or twice fundamental frequency

    for ZX Rate of 100 Hz and 60 seconds time, EGY_TIME is 0d5999

    You can use this formula when your accumulation is updated using the internal rate of the chip:

    Please refer to the page 50 of this document for more details and a complete guide that includes reset, INTEN bits, Fundamental frequency, zero crossing, and other status configurations.

    https://www.analog.com/media/en/technical-documentation/user-guides/ADE9000-UG-1098.pdf

    Hope this helps.

    Regards,

    Aaron

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