No, the EE-68 application note describing the ADI-recommended JTAG circuitry applies to all of ADI's processor portfolio up to and including the ADSP-BF60x family of dual-core Blackfin processors.
Beginning with the ADSP-BF70x Blackfin+ processors and carried forward to the recently announced ADSP-2158x/SC58x dual-core SHARC+ processors, the debug unit infrastructure block was changed to also support ARM technology. As such, an equivalent application note is currently being developed in support of these and future devices.
This post says the EE-68 document does not apply to the newer processors. Working on a design with SC587 now, and page 24 of its data sheet still references EE-68. The latest version on ADI's website of EE-68 is dated 2008, so it hasn't been updated. There are still obvious differences between EE-68 and the pins available on the SC587.
Anyone know more about the plans for ADI to update EE-68, if ever? Currently having difficulty getting boundary scan to work with the JTAG port on SC587, and having ADI point to incorrect documentation in response isn't helping.