Q
There is a statement in the Hardware Reference Manual that suggests that the
output state on the CANTX pin may be low if the muxed pin is configured as a
SPORT pin, which is the default state after reset. Since logic low is dominant
on the CAN bus, won't this always corrupt the CAN bus when the Blackfin starts
up?
A
This would only be an issue if the function enable register (PORT_FER) is
configured such that the CANTX and CANRX pins are being utilized as peripheral
pins rather than as GPIO pins before the port multiplex register (PORT_MUX) is
written to configure them as CAN pins instead of as SPORT pins. After reset,
the PORT_FER register defaults to all pins being GPIO, which means there is
nothing driven on those pins. As long as the PORT_MUX register is configured
for CAN use (by setting PJCE to b#01) before PORT_FER is written to have those
pins function as peripheral pins, there will not be a case where you are
driving dominant on CANTX due to misconfigured pins.