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Processors and DSP
Processors and DSP
Documents Speeding up flash programming using the command-line device programmer (cldp)
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Processors and DSP requires membership for participation - click to join
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  • 2 video cameras to the video decoder on the ADSP-BF561 Evaluation board?
  • 3 x EEPI on ADSP-BF548 processors?
  • ADSP-21363:  Wants to look it up in a j-tag chain and sitll use J-tag emulater
  • ADSP-21368 - WS Value
  • ADSP-21469 questions regarding PCN 11_0097 rev C
  • ADSp-BF532: I wish to read the odd 8bit registers must I always
  • ADSP-BF537: Is the BF537 kit able to do promiscuous mode?
  • ADSP-CM40x feature a Data Cache?
  • ADSp-TS201S: FFT difference in simulation and rel Time
  • Are MEMX and MEMY physical memories?
  • availability of default DSP Boot source code for the TigerSHARC
  • benchmarks for the TigerSHARC ADSP-TS201 Processor
  • BF537 supporting 8MB of FLASH?
  • BF561 SDK 2.01 : JPEG encoding from YUV422 format.
  • Blackfin CAN Pin operation after power-on
  • Blackfin processor and intrinsic (built-in) functions?
  • bus loading with the Blackfin BF533
  • Call and Jump instructions at the ADSP-TS101S
  • Can I access variables (in C code) defined in an external memory device
  • Can I Perform flash programming in SPI Memory Mapped mode?
  • Can I place DATA in CODE memory and vice-versa?
  • Can I use MATLAB and Simulink with the ADSP-CM40x and IAR Tool-chain?
  • CAN issue - remove frames
  • Changing IP address at run time
  • Chip Revision identification
  • Compiler needed for DSP
  • Configuration for slow Flash devices
  • connect my Blackfin EZ-Kit to a high speed converter (a few MHz) over the PPI Interface
  • Connected Devices Virtual Conference
  • connection of S1D13A05 Epson device to the ADSP-BF537
  • Core access of same variables at the ADSP-BF561
  • Count of Blackfin core clock cycles
  • Difference between SHARED_MEMORY{} and COMMON_MEMORY{} section commands
  • differences between the ADSP-BF537 and the ADSP-BF533 booting process
  • Disabling watchdog
  • DMA error conditions
  • Does the ADDS-USB-ICE include any software (on disk)
  • Does the JTAG Reference EE-68 Apply to the Newer Processors?
  • Driver Type E Specifications Missing from ADSP-BF60x Datasheet
  • duty cycle of the clock
  • dynamically turn off and on the instruction and/or data
  • Enabling Product-Specific Push Notifications from analog.com Web Site
  • FAQ: Define Nesting Interrupt concepts in Griffin Processor?
  • FAQ: Floating Power Pins on Processors
  • FAQ: How to add Compiler options with CCES GUI?
  • FAQ: How to use preprocessors in script for VDSP++5.0?
  • FAQ: ICE-1000 emulator does not recognize custom BF board
  • FAQ: Is available an elfloader.exe for the ADSP-CM408F?
  • FAQ: Is there a general overview on using the Disassembly window
  • FAQ: RoHS-Compliant Parts and Pin-Compatibility with Predecessors
  • floating point operations at Blackfin
  • free download limitations?
  • Heat sink recommendation for TigerSHARC ADSP-TS20xS
  • Hooking up interrupts in VDK for programming with Blackfin processors
  • Host Memory Mode on Blackfin Processors?
  • How can I utilize Cache with Async memory connected SRAM?
  • How can I utilize Cache with Async memory connected SRAM? (1)
  • How do I connect the Real Time Clock (RTC) pins on Blackfin?
  • How do I program the Blackfin PLL
  • How do I validate SPI on my newly designed board based on ADSP-SC58x/ADSP-2158x processors?
  • How do I validate the SPORT on my newly designed board based on ADSP-SC58x/ADSP-2158x processors?
  • How do I validate the UART on my newly designed board based on ADSP-SC58x/ADSP-2158x processors?
  • How do I validate TWI on my newly designed board based on ADSP-SC58x/ADSP-2158x processors?
  • Information for MPEG-4 for the ADSP-BF561
  • Intel's PCI_to_PCI bridge (21152) between the ADSP-BF535 and the PCI connector
  • junction temperature on the ADSP-TS101 TigerSHARC Processor
  • Link Port Cables for the ADSP-TS101 EZ-Kit Lite
  • Link Port Devices from ADI connected to the TigerSHARC Link Ports
  • LTSTAT/LRSTAT should be read twice sequentially to ensure correct value - anomaly 18730
  • Mobile SDRAM on BF533
  • MTBF and Other Data Required Data
  • MTBF of the ADSp-BF537
  • On-chip flash for ADSP-BF538F and ADSP-BF539F
  • performance of the Blackfin if program exceeds internal memory
  • physical address of the TEST_MODES register
  • Porting a VDK-project from Visual DSP++ 3.5 to 4.0
  • power-up sequencing for giving 3.3V and 1.2 V input supplies to ADSP-BF536/7
  • Problems with adequate heel fillets IPC
  • Problems with emulator session using floating license for VisualDSP++ 4.0?
  • Problems with the license after PC change
  • Processor Technical Support
  • PROCESSORS AND DSP SUPPORT COMMUNITY
  • prototyping the a ADSP-TS203S design with a ADSP-TS201s or a ADSP-TS202S
  • PWM example for the 21489 EZ-Kit board - Doesn't Exist
  • Questions 536 / VDK
  • RE: MDMA Issue with MPEG4 decoder Library (SR#: 0704922)
  • RE: Processor Technical Support (SR#: 0607855)
  • RE: Processor Technical Support (SR#: 0706904)
  • restrictions when communicating with the EZ kit via USB with no ICE on a test drive
  • schematic symbol, PCB footprint and layout information for the ADSP-TS201 TigerSHARC Processor Evaluation Board
  • Serial-termination resistors for the ext memory
  • solutioon for voice applications
  • Speech recognition on Blackfin and SHARC
  • Speeding up flash programming using the command-line device programmer (cldp)
  • Speex and Vorbis decoders
  • SPI framesync with /SPISS
  • SPI/Cache :: Line-Wrap mode vs. Line-base-first mode. Which one to choose?
  • TRST pin at the EZ-KITs
  • TS201 CJMP and PC problem
  • Updating ICE-1000/2000 firmware with OpenOCD
  • USB Voltage at the ADSF-BF53x USB
  • Using Flash with the Blackfin
  • Using the ADSP-BF533/2/1, is it possible to store programm code in SDRAM
  • Visual DSP++ Load driver error (ADSP-BF561 Flash Driver)
  • What do I need in order to evaluate the ADSP-CM40x Processors?
  • What is the EngineerZone URL location?
  • What is XiP?
  • Where Can I Find the Most Recent Silicon Revision for Processors and DSPs?
  • Where I can find information regarding reflow temperature profile for a particular processor?
  • [Bug Report] Sigma 'Hard Clip' in grown algorithm.
  • [FAQ] : How to suppress Misra rule checking for a particular file or a function?

Speeding up flash programming using the command-line device programmer (cldp)

There have been multiple comments/questions concerning the speed of the cldp programming. The provided flash programmer drivers that are used to program flash on Analog Devices Inc EZ-KITs are not optimized for programming speed. They are merely given as an example of how to program a flash device using the cldp and also to allow programming out of the box. There are definitely ways to speed up the programming process and those options will be outlined in this FAQ.

Increase buffer size

Most default ldf files only allow for a certain size heap which often limits the buffer size that the cldp can program during 1 transaction. For instance if a file is 1000 bytes and the buffer size is only 10 then 100 commands have to be sent from the cldp to the flash programmer driver running on the processor in order to transfer the entire buffer. It may be possible to increase this so that only 1 transaction is needed or maybe a handful. Users will have to determine the correct buffer size that gives the best performance boost. The buffer size variable that will need to be changed in the flash programmer driver is AFP_Size. Since there is only a certain amount of heap space by default and the buffer is created dynamically, users will have to take care to make sure they are not allocating too much memory for the amount of heap space that is allowed. Otherwise users would have to increase the heap size in the ldf file.

 

Increase SPI clock

The SPI clock used in the flash programmer driver may not be the max SPI clock for the device being programmed. The specification for the flash device found on the EZ-KIT should be used in order to find the max SPI clock allowed when programming the flash device. Once the max SPI clock is identified, reviewing the Hardware Reference manual will help with configuring the clock on the processor.

 

Change programming instruction

Many flash devices offer multiple programming options. Often the normal page program instruction is used but there may be other options that are faster. Consulting the instruction set table of the flash specification for other faster programming options would be recommended. There may be a dual page program or quad page program option available or possibly some other faster mechanism for programming flash that can be used.

 

Don't use -verify (v) option

By default when programming the verify option is NOT set. Please make sure that this option has not been added to the command line as it will slow down programming.

 

Upgrade emulators

If using the ICE-1000, ICE-100b, or USB-ICE emulators then upgrading to an HPUSB-ICE or ICE-2000 (latest emulator) would speed up programming as well.

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