Define Nesting Interrupt concepts in Griffin Processor?
It is defined as responding to another interrupt while a previous interrupt is being serviced.
Bits in the MODE1 and IMASKP registers control interrupt nesting as described below.
The NESTM bit in the MODE1 register directs the processor to enable (if 1) or disable (if 0) interrupt nesting.
When interrupt nesting is enabled, a higher priority interrupt can interrupt a lower priority interrupt's service routine. Lower priority interrupts are latched as they occur, but the processor processes them according to their priority after the nested routines finish.
The IMASKP bits in the IMASKP register list the interrupts in priority order and provide a temporary interrupt mask for each nesting level.