L1 Block2 PM in Sharc+ core

Q: L1 Block2 PM in Sharc+ core

Question: L1 Block2 PM in Sharc+ core Answer Code segments should not be placed in block2 when cache is enabled. There are two data caches (D-cache) and one instruction cache (I-cache) per SHARC+ core. The data cache is shared with (and uses) block1 which caches all the external memory access requests from the DM bus. Similarly, the other data cache is shared with (and uses) block2 which caches all external memory data access requests from the PM bus. Instruction cache is shared with (and uses) block3. The data cache used by the DM bus is referred to as DM cache and the data cache used by the PM bus is referred to as PM cache. So, by default l1 block2 is for PM data. Therefore, when the cache is enabled in the project, code segment should not be placed in block 2 However, if cache is disabled in project, then placing the code in block 2 works fine and doesn't have impact.

Question:
L1 Block2 PM in Sharc+ core

Answer
Code segments should not be placed in block2 when cache is enabled.

There are two data caches (D-cache) and one instruction cache (I-cache) per SHARC+ core. The data cache is shared with (and uses) block1 which caches all the external memory access requests from the DM bus. Similarly, the other data cache is shared with (and uses) block2 which caches all external memory data access requests from the PM bus. Instruction cache is shared with (and uses) block3. The data cache used by the DM bus is referred to as DM cache and the data cache used by the PM bus is referred to as PM cache.

So, by default l1 block2 is for PM data.

Therefore, when the cache is enabled in the project, code segment should not be placed in block 2 However, if cache is disabled in project, then placing the code in block 2 works fine and doesn't have impact.