What are the differences between the Compiled Simulator and the Cycle Accurate Simulator?
Visual DSP++ offers two different types of Simulator for each of the Blackfin processors; the Cycle Accurate Simulator and the Compiled Simulator. Although both of these Simulators are functionally correct, each has a separate application.
The Cycle Accurate Simulator is the only simulator suitable for use in determining the real-world performance of your application. This Simulator models latencies - such as Multi-Cycle Instructions, L1 Data Memory stalls and Instruction Latencies - allowing you to obtain real-world cycle counts and performance figures.
The Compiled Simulator is a separate simulation product shipped with VisualDSP++ that runs extremely fast at about 10MIPS (and is capable of faster speeds depending on the DXE and, of course, the speed and memory configuration of the workstation), compared to the Cycle Accurate Simulator which runs at around 20K CPS (Cycles per second). This simulator is more appropriate when running simulator sessions merely to test your code, where the speed of simulation does not have to be faithful to the real processor. For larger applications the improvement in simulation speed using the Compiled Simulator is significant compared to the Cycle Accurate Simulator.
The Compiled Simulator is deliberately not cycle accurate, as it is intended purely as a super-fast functional simulator. It does not model latencies and generally it does not account for them in the cycle count. That said, some latencies such as multi-cycle or change of control (calls & jumps) have been accounted for within the cycle counts so that the results of Profile Guided Optimization (PGO) are visible. Additionally, it should be noted that when using PGO on large signal chains (on any DXE that takes many millions/billions of instructions to complete) a compiled simulation session is the only option as the cycle accurate simulator is too slow.
Although cycle accuracy is forfeited with this simulator, functional correctness is not. It still supports the cycle counter because the register is present architecturally, but this should be considered more of an instruction counter than a cycle counter in the Compiled Simulator.
A typical approach is to use the Compiled Simulator when speed is essential and the Cycle Accurate Simulator when specific cycle accurate details are required. The Cycle Accurate Simulator is displayed as either the ADSP-BF5xx Single Processor Simulator or the ADSP-BF561 Dual Processor Simulator.
This FAQ was generated from the following thread: What are the differences between the Compiled Simulator and the Cycle Accurate Simulator?