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Unstable JTAG connection to target board


I have the analog devices ADZS-USB-ICE and trying to connect it to the ADSP BF504 on my DSP board.  May be 1 out of 10 times I can establish a connection but most of the time I can't.  Every time it failed to establish a connection I ran ICE test and all the tests passed (i.e.

Openning Emulator Interface -Pass

Resetting ICEPAC module -Pass

Testing ICEPAC memory -Pass

Determinging scan path length - (detects 1 device)

Performing scan test -Continous scan up to 10 Mbytes (Pass)

Even after ICE test passed, I still can not establish a sesstion in VDSP++.  I have checked all the power supply/ground pins, input clock to DSP, reset pin of DSP, PG pin (pull low), and Wake_up pin (high) and they all checked out.  Here are what I have checked:

ADSP BF504 (88pins):

VDDC (core voltate) = 1.2V

VDDIO (I/O voltage) = 2.5V

Reset Pin = Pull up high (10K to 2.5V)

PGn = Ground

clock in (pin 68): 12MHz

XTAL pin = no connection

Visual DSP/Emulator Setup:

Visual DSP++5.0 Update 10 (Product Version, IDDE version, Build Date: July 5, 2011)

Visual DSP++5.0 License:  Blackfin Demo-Full (Expiring in 37 days)

Visual DSP++5.0 Configuration (Type: USB-ICE, Emulator Settings Device ID: 0, Emulator Settings JTAG I/O Voltage: 2.5, Device 0 Type: ADSP-BF504, initial connection option:  Halt and reset.)

Deleted and installed the driver for the ADSP BF504 and still no help.  Deleted and re-create session and still no help.

Like I said, ICE test always passed but then unable to establish a conection (most of the time) to target board in Visual DSP++5.0 (always getting error code 0x80044005)



  • Hi Loc,

    we have an FAQ that covers the things we recommend checking on your target, here:

    FAQ:  Why does the ICE Test pass but IDDE cannot connect to target?

    If that does not help, you would need to contact private support so we can take a look at the JTAG portion of your schematics, and help figure out why it will not connect.



  • Hi,

    sounds very familiar...but I'm somewhat amazed that the recent VDSP releases still shows the same verbosity like in v3.0 when it comes to JTAG errors...

    There are a few things on my typical JTAG checklist:

    • traces to CPU from JTAG pod less than 7cm
    • no other clock signals (SCLK, SDRAM) near the TCK trace, check for good shielding
    • inserting a clock buffer (schmitt trigger) on TCK improves the HP-ICEs signal and avoids double clocking in noisy environments

    The JTAG pins go directly into the core silicon as far as I remember. So they need extremely sharp edges, means you have to do the typical high speed design even if you only clock TCK with a few MHz.

    Hope those hints help.


    - Martin

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