Compiler generates unaligned access instructions on a TS203

Hello all,

I'm working on a hardware that uses 2 TigerSHARC TS203 revision 2.0. The IDE is the version 5.0 update 10 of Visual DSP++ running on a Windows Vista PC. Optimization settings are at 100% (maximum speed).

Sometimes the optimiser chooses to generate an assembly instruction that accesses 2 adjacent variables (usually members of a C++ class instance) with one single instruction which looks like:

     XR3:2 = L[J3+0];

where J3 contains - I presume - the address of the lowest address word. In some occasion this address is odd (though the address of the C++ object instance is actually aligned on a 4 words boundary). When this instruction is executed the PC jumps to the SIGSEGV handler (sw_handler indeed). It appears that this handler implements the 2 words access and returns to the calling code silently. The drawback however is that it uses a large number of CPU cycles (some hundreds) which is something I cannot afford in the context this code is running in.

Does anyone know about a way to prevent the compiler to generate such instructions?