Category: Software
Product Number: ADSP-21565
Software Version: cces3.0.3 sigmastudio4.7
My custom board has two ADCs and two DACs, all TDM8, with a clock sampling rate of 96 kHz and 8-channel input/output. Therefore, I need to achieve 16-in 16-out audio performance. In my code, SPORT0A and 1B handle the first 8 channels, while SPORT2A and 5B handle the last 8 channels. After running my code, I downloaded a schematic of a 1 kHz sine wave output on 16 channels in SigmaStudio, but the output sine waves are very messy. I suspect that the data format or data processing is incorrect. Question 1: Is my SPORT configuration correct? Question 2: How should the data processing part in the main function's while loop be written? Question 3: For 96 kHz, besides modifying it in SigmaStudio, does the software part need to be changed?
/*****************************************************************************
* Audio_Loopback_TDM.c
*****************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <sys/platform.h>
#include <sys/adi_core.h>
#include "adi_initialize.h"
#include <services/int/adi_int.h>
#include <drivers/sport/adi_sport.h>
#include <services/pcg/adi_pcg.h>
#include <services/spu/adi_spu.h>
#include <drivers/twi/adi_twi_2156x.h>
#include "ADAU_1962Common.h"
#include "ADAU_1979Common.h"
#include <cdef21569.h>
#include "math.h"
#include <sru21569.h>
#include "LibIntegrationExample_Core1.h"
#include "adi_ss_smap.h"
#include "PowerServiceConfiguration.h"
/******* SigmaStudio Integration ***************/
/*Defining Backchannel info structure. Will be populated by the framework */
typedef struct ADI_SS_BACKCH_INFO
{
float32_t nPeakMIPS[ADI_SS_FW_MAX_PROC_BLOCKS]; /*!< Peak MIPS for all process blocks */
float32_t nAvgMIPS[ADI_SS_FW_MAX_PROC_BLOCKS]; /*!< Average MIPS for all process blocks */
uint32_t nVersionInfo; /*!< Target library API version */
uint32_t nSSnDownloadStatus; /*!< Current download status of SSns within all process blocks*/
}ADI_SS_BACKCH_INFO;
#include "adi_ss_connection.h"
#include "adi_ss_communication.h"
#include "adi_ss_ssn.h"
/* Memory for SigmaStudio for Griffin libraries */
/* Connection and Communication Instance Mem */
#pragma align(4)
#pragma section("ss_app_data0_fast")
uint8_t adi_ss_commn_mem[ADI_SS_COMM_MEMSIZE];
#pragma align(4)
#pragma section("ss_app_data0_fast")
uint8_t adi_ss_connection_mem[ADI_SS_CONNECTION_MEMSIZE];
bool bSportCallback;
volatile uint32_t nSMAPReceived=0;
/* SMAP */
ADI_SS_MEM_SMAP oSMAPSharc0;
ADI_SS_MEM_MAP oSSnMemMap;
/* SSn Config structure */
ADI_SS_CONFIG *pSSnConfig,oSSnConfig;
/* SSnProperties structure */
ADI_SS_SSNPROPERTIES *pSSnProperties,oSSnProperties;
/* Defining SSn Handle */
ADI_SS_SSN_HANDLE hSSnHandle;
/* Backchannel info */
ADI_SS_BACKCH_INFO oBkChannelInfoSharc0;
/* I/O buffer and pointers for SSn instance */
float32_t aSSInOutBuff[BLOCK_SIZE*NUM_CHANNELS];
float32_t *pSSInBuff[NUM_CHANNELS];
float32_t *pSSOutBuff[NUM_CHANNELS];
void adi_ss_comm_callback_cmd4(uint32_t *pCommPayloadBuff,
int32_t nPayloadCount,
ADI_SS_SSN_HANDLE hSSn);
void adi_SMAP_Application_Callback(ADI_SS_PROC_ID eCoreID);
/* Convert the audio samples generated by ADC into float format */
void CopyFix2Float( volatile uint32_t *pInBuffer,
uint32_t nInStride,
volatile float *pOutBuffer,
uint32_t nOutStride,
uint32_t nBlockSize,
uint32_t nShiftFlag);
/* Convert the audio samples from float to fixed point (which can be consumed by DAC) */
uint32_t CopyFloat2Fix(volatile float *pInBuffer,
uint32_t nInStride,
volatile uint32_t *pOutBuffer,
uint32_t nOutStride,
uint32_t nBlockSize,
uint32_t nShiftFlag);
/******* SigmaStudio Integration END ***************/
/* SPORT buffers */
int32_t int_SP0ABuffer1[BLOCK_SIZE*(NUM_CHANNELS/2)];
int32_t int_SP0ABuffer2[BLOCK_SIZE*(NUM_CHANNELS/2)];
int32_t int_SP0ABuffer4[BLOCK_SIZE*(NUM_CHANNELS/2)];
int32_t int_SP0ABuffer5[BLOCK_SIZE*(NUM_CHANNELS/2)];
int32_t int_SP0ABuffer6[BLOCK_SIZE * (NUM_CHANNELS/2)];
int32_t int_SP0ABuffer7[BLOCK_SIZE * (NUM_CHANNELS/2)];
int32_t int_SP0ABuffer8[BLOCK_SIZE * (NUM_CHANNELS/2)];
int32_t int_SP0ABuffer9[BLOCK_SIZE * (NUM_CHANNELS/2)];
struct Config_Table
{
short Reg_Add;
char Value;
};
char Config_read_DAC[28];
char Config_read_ADC[16];
static ADI_PWR_CGU_PARAM_LIST audio_cgu_params = {0};
static ADI_PWR_CDU_PARAM_LIST audio_cdu_params = {0};
/* Dev buffer for configuring ADC-DAC through TWI*/
static uint8_t devBuffer[BUFFER_SIZE];
extern void ConfigSoftSwitches_ADC_DAC(void);
extern void ConfigSoftSwitches_ADAU_Reset(void);
#if 0
struct Config_Table Config_array_DAC[28] = {
{ ADAU1962_PDN_CTRL_1, 0x00},
{ ADAU1962_PDN_CTRL_2, 0xff},
{ ADAU1962_PDN_CTRL_3, 0x0f},
{ ADAU1962_DAC_CTRL0, 0x01},
{ ADAU1962_DAC_CTRL1, 0x41},
{ ADAU1962_DAC_CTRL2, 0x00},
{ ADAU1962_DAC_MUTE1, 0x0},
{ ADAU1962_DAC_MUTE2, 0x00},
{ ADAU1962_MSTR_VOL, 0x00},
{ ADAU1962_DAC1_VOL, 0x00},
{ ADAU1962_DAC2_VOL, 0x00},
{ ADAU1962_DAC3_VOL, 0x00},
{ ADAU1962_DAC4_VOL, 0x00},
{ ADAU1962_DAC5_VOL, 0x00},
{ ADAU1962_DAC6_VOL, 0x00},
{ ADAU1962_DAC7_VOL, 0x00},
{ ADAU1962_DAC8_VOL, 0x00},
{ ADAU1962_DAC9_VOL, 0x00},
{ ADAU1962_DAC10_VOL, 0x00},
{ ADAU1962_DAC11_VOL, 0x00},
{ ADAU1962_DAC12_VOL, 0x00},
{ ADAU1962_PAD_STRGTH, 0x00},
{ ADAU1962_DAC_PWR1, 0xaa},
{ ADAU1962_DAC_PWR2, 0xaa},
{ ADAU1962_DAC_PWR3, 0xaa},
{ ADAU1962_PDN_CTRL_2, 0x00},
{ ADAU1962_PDN_CTRL_3, 0x00},
{ ADAU1962_DAC_CTRL0, 0x18}
};
#else
struct Config_Table Config_array_DAC[28] = {
{ ADAU1962_PDN_CTRL_1, 0xa4 },
{ ADAU1962_PDN_CTRL_2, 0xff }, //Power down DAC
{ ADAU1962_PDN_CTRL_3, 0x0f }, //Power down DAC
{ ADAU1962_DAC_CTRL0, 0x19 },
{ ADAU1962_DAC_CTRL1, 0x63 }, // pulse mode LRCLK, MSB first //orginal value =42
{ ADAU1962_DAC_CTRL2, 0x04 }, // TDM Configuration
{ ADAU1962_DAC_MUTE1, 0x00 },
{ ADAU1962_DAC_MUTE2, 0x00 },
{ ADAU1962_MSTR_VOL, 0x00 },
{ ADAU1962_DAC1_VOL, 0x00 } ,
{ ADAU1962_DAC2_VOL, 0x00 },
{ ADAU1962_DAC3_VOL, 0x00 },
{ ADAU1962_DAC4_VOL, 0x00 },
{ ADAU1962_DAC5_VOL, 0x00 },
{ ADAU1962_DAC6_VOL, 0x00 },
{ ADAU1962_DAC7_VOL, 0x00 },
{ ADAU1962_DAC8_VOL, 0x00 },
{ ADAU1962_DAC9_VOL, 0x00 },
{ ADAU1962_DAC10_VOL, 0x00 },
{ ADAU1962_DAC11_VOL, 0x00 },
{ ADAU1962_DAC12_VOL, 0x00 },
{ ADAU1962_PAD_STRGTH, 0x00 },
{ ADAU1962_DAC_PWR1, 0xaa },
{ ADAU1962_DAC_PWR2, 0xaa },
{ ADAU1962_DAC_PWR3, 0xaa },
{ ADAU1962_PDN_CTRL_2, 0x00 },
{ ADAU1962_PDN_CTRL_3, 0x00 },
{ ADAU1962_DAC_CTRL0, 0x18 },
};
#endif
#if 0
struct Config_Table Config_array_ADC[16] = {
{ADAU1979_REG_BOOST , 0x00},
{ADAU1979_REG_MICBIAS , 0x00},
{ADAU1979_REG_BLOCK_POWER_SAI , 0x30},
/*{ADAU1979_REG_SAI_CTRL0 , 0x1B}, */
{ADAU1979_REG_SAI_CTRL0 , 0x1A},/*I2S format*/
{ADAU1979_REG_SAI_CTRL1 , 0x08},
{ADAU1979_REG_CMAP12 , 0x10},
{ADAU1979_REG_CMAP34 , 0x32},
{ADAU1979_REG_SAI_OVERTEMP , 0xf0},
{ADAU1979_REG_POST_ADC_GAIN1 , 0xA0},
{ADAU1979_REG_POST_ADC_GAIN2 , 0xA0},
{ADAU1979_REG_POST_ADC_GAIN3 , 0xA0},
{ADAU1979_REG_POST_ADC_GAIN4 , 0xA0},
{ADAU1979_REG_ADC_CLIP , 0x00},
{ADAU1979_REG_DC_HPF_CAL , 0x00},
{ADAU1979_REG_BLOCK_POWER_SAI , 0x3f},
{ADAU1979_REG_MISC_CONTROL , 0x02}
};
#else
struct Config_Table Config_array_ADC[16] = {
{ADAU1979_REG_BOOST , 0x00},
{ADAU1979_REG_MICBIAS , 0x00},
{ADAU1979_REG_BLOCK_POWER_SAI , 0xb0},//power down ADC LDO enabel
{ADAU1979_REG_SAI_CTRL0 , 0x5a},//TDM 48kHz
{ADAU1979_REG_SAI_CTRL1 , 0x08},//LRCLK pulse mode //original value =08
{ADAU1979_REG_CMAP12 , 0x10},
{ADAU1979_REG_CMAP34 , 0x32},
{ADAU1979_REG_SAI_OVERTEMP , 0xf0},
{ADAU1979_REG_POST_ADC_GAIN1 , 0xA0},
{ADAU1979_REG_POST_ADC_GAIN1 , 0xA0},
{ADAU1979_REG_POST_ADC_GAIN3 , 0xA0},
{ADAU1979_REG_POST_ADC_GAIN4 , 0xA0},
{ADAU1979_REG_ADC_CLIP , 0x00},
{ADAU1979_REG_DC_HPF_CAL , 0x00},// filter off
{ADAU1979_REG_BLOCK_POWER_SAI , 0xbf},//power on ADC LDO enable
{ADAU1979_REG_MISC_CONTROL , 0x02},//mute all channels
};
#endif
/* Destination PDMA lists */
ADI_PDMA_DESC_LIST iDESC_LIST_1_SP2A;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP2A ;
ADI_PDMA_DESC_LIST iDESC_LIST_1_SP0A;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP0A ;
/* Source PDMA lists */
ADI_PDMA_DESC_LIST iSRC_LIST_1_SP5B ;
ADI_PDMA_DESC_LIST iSRC_LIST_2_SP5B ;
ADI_PDMA_DESC_LIST iSRC_LIST_1_SP1B ;
ADI_PDMA_DESC_LIST iSRC_LIST_2_SP1B ;
/* Prepares descriptors for SPORT DMA */
static void PrepareDescriptors (void);
/* Count to track the number of callBacks for SPORT transfer */
volatile uint8_t CallbackCount = 0;
volatile uint32_t TestCallbackCount = 0;
volatile uint32_t nDataAvail=0;
/* Memory required for SPORT */
static uint8_t SPORTMemory2A[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory5B[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory0A[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory1B[ADI_SPORT_MEMORY_SIZE];
/* SPORT Handle */
static ADI_SPORT_HANDLE hSPORTDev2ATx;//TX
static ADI_SPORT_HANDLE hSPORTDev5BRx;//RX
static ADI_SPORT_HANDLE hSPORTDev0ATx;//TX
static ADI_SPORT_HANDLE hSPORTDev1BRx;//RX
/* Memory required for TWI */
uint8_t TwideviceMemory[ADI_TWI_MEMORY_SIZE];
/* TWI driver handle */
static ADI_TWI_HANDLE hTwiDevice;
/* SPU handle */
static ADI_SPU_HANDLE ghSpu;
/* Memory required for the SPU operation */
uint8_t SpuMemory[ADI_SPU_MEMORY_SIZE];
int32_t delay;
static int32_t ADAU_1962_Pllinit(void);
static int32_t ADAU_1979_Pllinit(void);
void Switch_Configurator(void);
static int32_t ADAU_1962_init(void);
static int32_t ADAU_1979_init(void);
void SRU_Init(void);
static int32_t Sport_Init(void);
static int32_t Sport_Stop(void);
static int32_t SPU_init(void);
static void PrepareDescriptors (void);
static int32_t Init_TWI(void);
static int32_t Stop_TWI(void);
void PCG_init(void);
static void SPORTCallback(void *pAppHandle,
uint32_t nEvent,
void *pArg
)
{
int32_t i;
int32_t j;
ADI_SPORT_RESULT eResult;
/* CASEOF (event type) */
switch (nEvent)
{
/* CASE (buffer processed) */
case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
TestCallbackCount += 1;
CallbackCount += 1;
nDataAvail += 1;
break;
default:
break;
}
/* return */
}
uint32_t adi_pwr_audio_config(void)
{
ADI_PWR_CGU_PARAM_LIST pADI_CGU_Param_List;
ADI_PWR_CDU_PARAM_LIST pADI_CDU_Param_List;
audio_cgu_params.cgu0_settings.clocksettings.ctl_MSEL = 50; // PLL=CLKIN*MSEL
audio_cgu_params.cgu0_settings.clocksettings.ctl_DF = 0; // DF=0
audio_cgu_params.cgu0_settings.clocksettings.div_CSEL = 5; // CCLK = PLL/CCLK =
audio_cgu_params.cgu0_settings.clocksettings.div_SYSSEL = 5; // SYSCLK = CCLK/SYSSEL =
audio_cgu_params.cgu0_settings.clocksettings.div_S0SEL = 2; // SCLK0 = SYSCLK/S0SEL =
audio_cgu_params.cgu0_settings.clocksettings.div_DSEL = 3; // DCLK = PLLCLK/6 ≈
audio_cgu_params.cgu0_settings.clocksettings.div_OSEL = 8; // OCLK = PLLCLK/16 =
audio_cgu_params.cgu0_settings.clkin = 24576000; // 25MHz输入
/* 2. 配置CDU参数 - 使用SCLK0作为CLKO0输出 */
audio_cdu_params.cdu_settings[0].cfg_SEL = 0; // 对应SCLK0_0
audio_cdu_params.cdu_settings[0].cfg_EN = true;
/* 3. 初始化时钟系统 - 仅使用CGU0 */
audio_cgu_params.cgu1_settings.clocksettings.ctl_MSEL = 0; // 禁用CGU1
/* 调用原文件中的时钟初始化函数 */
if(adi_pwr_ClockInit(&audio_cgu_params, &audio_cdu_params) != ADI_PWR_SUCCESS)
{
return 1u; // 初始化失败
}
return 0u; // 初始化成功
}
/* 主配置函数 */
uint32_t adi_pwr_cfg0_init(void)
{
/* 调用自定义音频配置 */
if(adi_pwr_audio_config() != 0u)
{
return 1u;
}
return 0u;
}
void PCG_init(void)
{
ADI_PCG_CLK_INFO gClkInfoA = {
ADI_PCG_CLK_SCLK0, // Clock Source
5, // Clock Divisor
false // External Trigger
};
ADI_PCG_FS_INFO gFsInfoA = {
ADI_PCG_FS_SCLK0, // Clock Source
1280, // Frame Sync Divisor (256 for 48kHz)
640, // Pulse Width (16 slots * 32 bits)
0, // Phase
false, // External Trigger
ADI_PCG_FSBYPASS_MODE_NORMAL // Bypass Mode
};
ADI_PCG_CLK_INFO gClkInfoC = {
ADI_PCG_CLK_SCLK0, // Clock Source
5, // Clock Divisor
false // External Trigger
};
ADI_PCG_FS_INFO gFsInfoC = {
ADI_PCG_FS_SCLK0, // Clock Source
1280, // Frame Sync Divisor (256 for 48kHz)
640, // Pulse Width (16 slots * 32 bits)
0, // Phase
false, // External Trigger
ADI_PCG_FSBYPASS_MODE_NORMAL // Bypass Mode
};
ADI_PCG_CLK_INFO gClkInfoB = {
ADI_PCG_CLK_SCLK0, // Clock Source
5, // Clock Divisor
false // External Trigger
};
ADI_PCG_FS_INFO gFsInfoB = {
ADI_PCG_FS_SCLK0, // Clock Source
1280, // Frame Sync Divisor (256 for 48kHz)
640, // Pulse Width (16 slots * 32 bits)
0, // Phase
false, // External Trigger
ADI_PCG_FSBYPASS_MODE_NORMAL // Bypass Mode
};
adi_pcg_Init(ADI_PCG_DEV_A, &gClkInfoA, &gFsInfoA);
adi_pcg_Init(ADI_PCG_DEV_B, &gClkInfoB, &gFsInfoB);
adi_pcg_Init(ADI_PCG_DEV_C, &gClkInfoC, &gFsInfoC);
}
/*
* Prepares descriptors for Memory DMA copy.
*
* Parameters
* None
*
* Returns
* None
*
*/
static void PrepareDescriptors (void)
{
iDESC_LIST_1_SP0A.pStartAddr = (int32_t *)int_SP0ABuffer1;
iDESC_LIST_1_SP0A.Config = ENUM_DMA_CFG_XCNT_INT ;
iDESC_LIST_1_SP0A.XCount = BLOCK_SIZE*NUM_CHANNELS;
iDESC_LIST_1_SP0A.XModify = 4;
iDESC_LIST_1_SP0A.YCount = 0;
iDESC_LIST_1_SP0A.YModify = 0;
iDESC_LIST_1_SP0A.pNxtDscp = &iDESC_LIST_2_SP0A;
iDESC_LIST_2_SP0A.pStartAddr = (int32_t *)int_SP0ABuffer2;
iDESC_LIST_2_SP0A.Config = ENUM_DMA_CFG_XCNT_INT ;
iDESC_LIST_2_SP0A.XCount = BLOCK_SIZE*(NUM_CHANNELS/2);
iDESC_LIST_2_SP0A.XModify = 4;
iDESC_LIST_2_SP0A.YCount = 0;
iDESC_LIST_2_SP0A.YModify = 0;
iDESC_LIST_2_SP0A.pNxtDscp = &iDESC_LIST_1_SP0A;
iSRC_LIST_1_SP1B.pStartAddr =(int32_t *)int_SP0ABuffer4;
iSRC_LIST_1_SP1B.Config = ENUM_DMA_CFG_XCNT_INT ;
iSRC_LIST_1_SP1B.XCount = BLOCK_SIZE*(NUM_CHANNELS/2);
iSRC_LIST_1_SP1B.XModify = 4;
iSRC_LIST_1_SP1B.YCount = 0;
iSRC_LIST_1_SP1B.YModify = 0;
iSRC_LIST_1_SP1B.pNxtDscp = &iSRC_LIST_2_SP1B;
iSRC_LIST_2_SP1B.pStartAddr =(int32_t *)int_SP0ABuffer5;
iSRC_LIST_2_SP1B.Config = ENUM_DMA_CFG_XCNT_INT;
iSRC_LIST_2_SP1B.XCount = BLOCK_SIZE*(NUM_CHANNELS/2);
iSRC_LIST_2_SP1B.XModify = 4;
iSRC_LIST_2_SP1B.YCount = 0;
iSRC_LIST_2_SP1B.YModify = 0;
iSRC_LIST_2_SP1B.pNxtDscp = &iSRC_LIST_1_SP1B;
iDESC_LIST_1_SP2A.pStartAddr = (int32_t *)int_SP0ABuffer6;
iDESC_LIST_1_SP2A.Config = ENUM_DMA_CFG_XCNT_INT ;
iDESC_LIST_1_SP2A.XCount = BLOCK_SIZE*(NUM_CHANNELS/2);
iDESC_LIST_1_SP2A.XModify = 4;
iDESC_LIST_1_SP2A.YCount = 0;
iDESC_LIST_1_SP2A.YModify = 0;
iDESC_LIST_1_SP2A.pNxtDscp = &iDESC_LIST_2_SP2A;
iDESC_LIST_2_SP2A.pStartAddr = (int32_t *)int_SP0ABuffer7;
iDESC_LIST_2_SP2A.Config = ENUM_DMA_CFG_XCNT_INT ;
iDESC_LIST_2_SP2A.XCount = BLOCK_SIZE*(NUM_CHANNELS/2);
iDESC_LIST_2_SP2A.XModify = 4;
iDESC_LIST_2_SP2A.YCount = 0;
iDESC_LIST_2_SP2A.YModify = 0;
iDESC_LIST_2_SP2A.pNxtDscp = &iDESC_LIST_1_SP2A;
iSRC_LIST_1_SP5B.pStartAddr =(int32_t *)int_SP0ABuffer8;
iSRC_LIST_1_SP5B.Config = ENUM_DMA_CFG_XCNT_INT ;
iSRC_LIST_1_SP5B.XCount = BLOCK_SIZE*(NUM_CHANNELS/2);
iSRC_LIST_1_SP5B.XModify = 4;
iSRC_LIST_1_SP5B.YCount = 0;
iSRC_LIST_1_SP5B.YModify = 0;
iSRC_LIST_1_SP5B.pNxtDscp = &iSRC_LIST_2_SP5B;
iSRC_LIST_2_SP5B.pStartAddr =(int32_t *)int_SP0ABuffer9;
iSRC_LIST_2_SP5B.Config = ENUM_DMA_CFG_XCNT_INT;
iSRC_LIST_2_SP5B.XCount = BLOCK_SIZE*(NUM_CHANNELS/2);
iSRC_LIST_2_SP5B.XModify = 4;
iSRC_LIST_2_SP5B.YCount = 0;
iSRC_LIST_2_SP5B.YModify = 0;
iSRC_LIST_2_SP5B.pNxtDscp = &iSRC_LIST_1_SP5B;
}
static int32_t Sport_Init()
{
/* SPORT return code */
ADI_SPORT_RESULT eResult;
/* Open the SPORT Device 4A */
eResult = adi_sport_Open(SPORT_DEVICE_0A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_MC_MODE, SPORTMemory0A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev0ATx);
CHECK_RESULT(eResult);
/* Open the SPORT Device 4B*/
eResult = adi_sport_Open(SPORT_DEVICE_1B,ADI_HALF_SPORT_B,ADI_SPORT_DIR_RX, ADI_SPORT_MC_MODE, SPORTMemory1B,ADI_SPORT_MEMORY_SIZE,&hSPORTDev1BRx);
CHECK_RESULT(eResult);
eResult = adi_sport_Open(SPORT_DEVICE_2A, ADI_HALF_SPORT_A, ADI_SPORT_DIR_TX,ADI_SPORT_MC_MODE, SPORTMemory2A, ADI_SPORT_MEMORY_SIZE, &hSPORTDev2ATx);
CHECK_RESULT(eResult);
eResult = adi_sport_Open(SPORT_DEVICE_5B, ADI_HALF_SPORT_B, ADI_SPORT_DIR_RX,ADI_SPORT_MC_MODE, SPORTMemory5B, ADI_SPORT_MEMORY_SIZE, &hSPORTDev5BRx);
CHECK_RESULT(eResult);
/* Configure the data,clock,frame sync and MCTL of SPORT Device 4A*/
eResult = adi_sport_ConfigData(hSPORTDev0ATx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigClock(hSPORTDev0ATx,32,false,/*false*/ false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigFrameSync(hSPORTDev0ATx,31,false,false,false,/*true*/ true,false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigMC(hSPORTDev0ATx,1u,7u,0u,true);
CHECK_RESULT(eResult);
eResult = adi_sport_SelectChannel(hSPORTDev0ATx,0u,7u);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigData(hSPORTDev2ATx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigClock(hSPORTDev2ATx,32,false,/*false*/ false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigFrameSync(hSPORTDev2ATx,31,false,false,false,/*true*/ true,false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigMC(hSPORTDev2ATx,1u,7u,0u,true);
CHECK_RESULT(eResult);
eResult = adi_sport_SelectChannel(hSPORTDev2ATx,0u,7u);
CHECK_RESULT(eResult);
/* Configure the data,clock,frame sync and MCTL of SPORT Device 4B*/
eResult = adi_sport_ConfigData(hSPORTDev1BRx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigClock(hSPORTDev1BRx,32,false,/*false*/ false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigFrameSync(hSPORTDev1BRx,31,false,false,false,/*true*/ true,false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigMC(hSPORTDev1BRx,1u,7u,0u,false);
CHECK_RESULT(eResult);
eResult = adi_sport_SelectChannel(hSPORTDev1BRx,0u,7u);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigData(hSPORTDev5BRx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigClock(hSPORTDev5BRx,32,false,/*false*/ false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigFrameSync(hSPORTDev5BRx,31,false,false,false,/*true*/ true,false,false);
CHECK_RESULT(eResult);
eResult = adi_sport_ConfigMC(hSPORTDev5BRx,1u,7u,0u,false);
CHECK_RESULT(eResult);
eResult = adi_sport_SelectChannel(hSPORTDev5BRx,0u,7u);
CHECK_RESULT(eResult);
/* Register SPORT Callback function */
eResult = adi_sport_RegisterCallback(hSPORTDev1BRx,SPORTCallback,NULL);
CHECK_RESULT(eResult);
eResult = adi_sport_RegisterCallback(hSPORTDev5BRx,SPORTCallback,NULL);
CHECK_RESULT(eResult);
/* Prepare descriptors */
PrepareDescriptors();
/* Submit the first buffer for Rx. */
eResult = adi_sport_DMATransfer(hSPORTDev1BRx,&iSRC_LIST_1_SP1B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
CHECK_RESULT(eResult);
eResult = adi_sport_DMATransfer(hSPORTDev5BRx,&iSRC_LIST_1_SP5B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
CHECK_RESULT(eResult);
/* Submit the first buffer for Tx. */
eResult = adi_sport_DMATransfer(hSPORTDev0ATx,&iDESC_LIST_1_SP0A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
CHECK_RESULT(eResult);
/* Submit the first buffer for Tx. */
eResult = adi_sport_DMATransfer(hSPORTDev2ATx,&iDESC_LIST_1_SP2A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
CHECK_RESULT(eResult);
/*Enable the Sport Device 4B */
eResult = adi_sport_Enable(hSPORTDev1BRx,true);
CHECK_RESULT(eResult);
eResult = adi_sport_Enable(hSPORTDev5BRx,true);
CHECK_RESULT(eResult);
/*Enable the Sport Device 4A */
eResult = adi_sport_Enable(hSPORTDev2ATx,true);
CHECK_RESULT(eResult);
eResult = adi_sport_Enable(hSPORTDev0ATx,true);
CHECK_RESULT(eResult);
return eResult;
}
static int32_t Sport_Stop(void)
{
/* SPORT return code */
ADI_SPORT_RESULT eResult;
/*Stop the DMA transfer of Sport Device 4B */
eResult = adi_sport_StopDMATransfer(hSPORTDev1BRx);
CHECK_RESULT(eResult);
/*Stop the DMA transfer of Sport Device 4A */
eResult = adi_sport_StopDMATransfer(hSPORTDev0ATx);
CHECK_RESULT(eResult);
/*Stop the DMA transfer of Sport Device 4B */
eResult = adi_sport_StopDMATransfer(hSPORTDev5BRx);
CHECK_RESULT(eResult);
/*Stop the DMA transfer of Sport Device 4A */
eResult = adi_sport_StopDMATransfer(hSPORTDev2ATx);
CHECK_RESULT(eResult);
/*Close Sport Device 4B */
eResult = adi_sport_Close(hSPORTDev1BRx);
CHECK_RESULT(eResult);
/*Close Sport Device 4A */
eResult = adi_sport_Close(hSPORTDev0ATx);
CHECK_RESULT(eResult);
eResult = adi_sport_Close(hSPORTDev5BRx);
CHECK_RESULT(eResult);
/*Close Sport Device 4A */
eResult = adi_sport_Close(hSPORTDev2ATx);
CHECK_RESULT(eResult);
return eResult;
}
/*
* Prepares Switch configuration.
*
* Parameters
* None
*
* Returns
* None
*
*/
void Switch_Configurator()
{
int32_t delay11=0xffff;
/* Software Switch Configuration for Re-Setting ADC-DAC */
ConfigSoftSwitches_ADAU_Reset();
while(delay11--)
{
asm("nop;");
}
/* Software Switch Configuration for Enabling ADC-DAC */
ConfigSoftSwitches_ADC_DAC();
/* wait for Codec to up */
delay11=0xffff;
while(delay11--)
{
asm("nop;");
}
}
/*
* Prepares SRU configuration.
*
* Parameters
* None
*
* Returns
* None
*
*/
void SRU_Init()
{
*pREG_PADS0_DAI0_IE=0xfffff;
*pREG_PADS0_DAI1_IE=0xfffff;
SRU(LOW,DAI0_PBEN01_I);
SRU(LOW,DAI0_PBEN02_I);
SRU(LOW,DAI0_PBEN03_I);
SRU(LOW,DAI0_PBEN04_I);
SRU(LOW,DAI0_PBEN05_I);
SRU(HIGH,DAI0_PBEN06_I);
SRU(HIGH,DAI0_PBEN07_I);
SRU(HIGH,DAI0_PBEN08_I);
SRU(HIGH,DAI0_PBEN09_I);
SRU(HIGH,DAI0_PBEN10_I);
SRU(HIGH,DAI0_PBEN19_I);
SRU(HIGH,DAI0_PBEN20_I);
SRU2(LOW,DAI1_PBEN01_I);
SRU2(LOW,DAI1_PBEN02_I);
SRU2(LOW,DAI1_PBEN03_I);
SRU2(LOW,DAI1_PBEN04_I);
SRU2(LOW,DAI1_PBEN05_I);
SRU2(LOW,DAI1_PBEN06_I);
SRU2(HIGH,DAI1_PBEN07_I);
SRU2(HIGH,DAI1_PBEN08_I);
SRU2(LOW,DAI1_PBEN09_I);
SRU2(LOW,DAI1_PBEN10_I);
SRU2(LOW,DAI1_PBEN19_I);
SRU2(LOW,DAI1_PBEN20_I);
SRU(PCG0_FSA_O, DAI0_PB08_I);//DAC LRCLK
SRU(PCG0_CLKA_O, DAI0_PB06_I);//DAC MCLK
SRU(PCG0_CLKA_O, DAI0_PB07_I);//DAC BCLK
SRU(PCG0_CLKA_O, SPT0_ACLK_I);
SRU(PCG0_FSA_O, SPT0_AFS_I);
SRU(PCG0_CLKA_O, SPT0_BCLK_I);
SRU(PCG0_FSA_O, SPT0_BFS_I);
SRU(PCG0_CLKA_O, SPT2_ACLK_I);
SRU(PCG0_FSA_O, SPT2_AFS_I);
SRU2(PCG0_CLKC_O, SPT5_BCLK_I);
SRU2(PCG0_FSC_O, SPT5_BFS_I);
SRU2(DAI1_PB06_O, SPT5_BD0_I);//ADC1 DATA IN
SRU(DAI0_PB02_O, SPT0_BD0_I);//ADC2 DATA IN
//SRU2(DAI0_PB04_O, SPT0_BD0_I);
//SRU2(SPT0_AD0_O, DAI0_PB19_I);
SRU(SPT0_AD0_O, DAI0_PB09_I);//DAC1 DATA OUT
SRU(SPT2_AD0_O, DAI0_PB19_I);//DAC2 DATA OUT
}
/*
* Prepares SPU configuration.
*
* Parameters
* None
*
* Returns
* None
*
*/
int32_t SPU_init(void)
{
if(adi_spu_Init(0, SpuMemory, NULL, NULL, &ghSpu) != ADI_SPU_SUCCESS)
{
REPORT_ERROR("Failed to initialize SPU service\n");
return FAILED;
}
/* Make SPORT 0A to generate secure transactions */
if(adi_spu_EnableMasterSecure(ghSpu, SPORT_0A_SPU, true) != ADI_SPU_SUCCESS)
{
REPORT_ERROR("Failed to enable Master secure for SPORT0A\n");
return FAILED;
}
/* Make SPORT 0B to generate secure transactions */
if(adi_spu_EnableMasterSecure(ghSpu, SPORT_1B_SPU, true) != ADI_SPU_SUCCESS)
{
REPORT_ERROR("Failed to enable Master secure for SPORT0B\n");
return FAILED;
}
if(adi_spu_EnableMasterSecure(ghSpu, SPORT_2A_SPU, true) != ADI_SPU_SUCCESS)
{
REPORT_ERROR("Failed to enable Master secure for SPORT0A\n");
return FAILED;
}
/* Make SPORT 0B to generate secure transactions */
if(adi_spu_EnableMasterSecure(ghSpu, SPORT_5B_SPU, true) != ADI_SPU_SUCCESS)
{
REPORT_ERROR("Failed to enable Master secure for SPORT0B\n");
return FAILED;
}
return SUCCESS;
}
void Write_TWI_8bit_Reg(unsigned char Reg_ID, unsigned char Tx_Data)
{
devBuffer[0] = Reg_ID;
devBuffer[1] = Tx_Data;
adi_twi_Write(hTwiDevice, devBuffer, 2u, false);
}
uint8_t Read_TWI_8bit_Reg(unsigned char Reg_ID)
{
ADI_TWI_RESULT eResult;
uint8_t Rx_Data;
/* write register address */
devBuffer[0] = Reg_ID;
eResult = adi_twi_Write(hTwiDevice, devBuffer, 1u, true);
if(eResult!=ADI_TWI_SUCCESS)
{
//REPORT_ERROR("TWI write failed 0x%08X\n", eResult);
}
/* read register value */
eResult = adi_twi_Read(hTwiDevice, &Rx_Data, 1u, false);
if(eResult!=ADI_TWI_SUCCESS)
{
//REPORT_ERROR("TWI Read failed 0x%08X\n", eResult);
}
return Rx_Data;
}
static int32_t Init_TWI(void)
{
ADI_TWI_RESULT eResult;
eResult = adi_twi_Open(TWIDEVNUM, ADI_TWI_MASTER, &TwideviceMemory[0],
ADI_TWI_MEMORY_SIZE, &hTwiDevice);
if(eResult!=ADI_TWI_SUCCESS)
{
//REPORT_ERROR("TWI Open failed 0x%08X\n", eResult);
}
eResult = adi_twi_SetPrescale(hTwiDevice, PRESCALEVALUE);
if(eResult!=ADI_TWI_SUCCESS)
{
//REPORT_ERROR("TWI Set Prescale failed 0x%08X\n", eResult);
}
eResult = adi_twi_SetBitRate(hTwiDevice, BITRATE);
if(eResult!=ADI_TWI_SUCCESS)
{
//REPORT_ERROR("TWI Set Bitrate failed 0x%08X\n", eResult);
}
eResult = adi_twi_SetDutyCycle(hTwiDevice, DUTYCYCLE);
if(eResult!=ADI_TWI_SUCCESS)
{
//REPORT_ERROR("TWI Set Duty cycle failed 0x%08X\n", eResult);
}
eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR);
if(eResult!=ADI_TWI_SUCCESS)
{
//REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
}
return eResult;
}
static int32_t Stop_TWI(void)
{
ADI_TWI_RESULT eResult;
eResult = adi_twi_Close(hTwiDevice);
CHECK_RESULT(eResult);
return eResult;
}
/*****************************************************************************************************************************/
static int32_t ADAU_1962_init(void)
{
int32_t i;
ADAU_1962_Pllinit();
for(i=0;i<28;i++)
{
/* write value */
Write_TWI_8bit_Reg(Config_array_DAC[i].Reg_Add,Config_array_DAC[i].Value);
Config_read_DAC[i]=Read_TWI_8bit_Reg(Config_array_DAC[i].Reg_Add);
if(Config_array_DAC[i].Value!= Config_read_DAC[i])
{
DEBUG_INFORMATION("\n Configuring ADAU_1962 failed");
return FAILED;
}
}
return SUCCESS;
}
static int32_t ADAU_1962_Pllinit(void)
{
int32_t status,delay1=0xffff;
ADI_TWI_RESULT eResult;
eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR_1962);
if(eResult!=ADI_TWI_SUCCESS)
{
//REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
}
Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x01);
while(delay1--)
{
asm("nop;");
}
Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x05);
delay1=0xffff;
while(delay1--)
{
asm("nop;");
}
Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1,0x22);
delay1=0xffff;
while(delay1--)
{
asm("nop;");
}
status=Read_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1);
while(!((status & 0x4)>>2) )
{
status=Read_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1);
}
return eResult;
}
static int32_t ADAU_1979_init(void)
{
int32_t i;
ADAU_1979_Pllinit();
for(i=0; i<16; i++)
{
Write_TWI_8bit_Reg(Config_array_ADC[i].Reg_Add,Config_array_ADC[i].Value);
Config_read_ADC[i]=Read_TWI_8bit_Reg(Config_array_ADC[i].Reg_Add);
if(Config_array_ADC[i].Value!= Config_read_ADC[i])
{
DEBUG_INFORMATION("\n Configuring ADAU_1979 failed");
return FAILED;
}
}
return SUCCESS;
}
static int32_t ADAU_1979_Pllinit(void)
{
int32_t status,delay1=0xffff;
ADI_TWI_RESULT eResult;
eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR_1979);
if(eResult!=ADI_TWI_SUCCESS)
{
//REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
}
Write_TWI_8bit_Reg(ADAU1979_REG_POWER,0x01);
Write_TWI_8bit_Reg(ADAU1979_REG_PLL,0x03);
status=Read_TWI_8bit_Reg(ADAU1979_REG_PLL);
while(delay1--)
{
asm("nop;");
}
while(!((status & 0x80)>>7) )
{
status=Read_TWI_8bit_Reg(ADAU1979_REG_PLL);
asm("nop;");
}
return eResult;
}
//#define BYPASS_SS
int32_t nTempBuff[BLOCK_SIZE*NUM_CHANNELS];
void main(int32_t argc, char *argv[])
{
/**
* Initialize managed drivers and/or services that have been added to
* the project.
* @return zero on success
*/
uint32_t Result=0, i, j;
ADI_SS_MEM_BLOCK oConnectionMemBlk, *pConnectionMemBlk;
ADI_SS_CONNECTION_CONFIG oConnConfig, *pConnConfig;
ADI_SS_CONNECTION_RESULT eConnRet = ADI_SS_CONNECTION_FAILED;
ADI_SS_CONNECTION_HANDLE hConnHandle;
ADI_SS_MEM_BLOCK oCommMemBlk, *pCommMemBlk;
ADI_SS_COMM_CONFIG oCommnConfig, *pCommnConfig;
ADI_SS_COMM_RESULT eCommRet = ADI_SS_COMM_FAILED;
ADI_SS_COMM_HANDLE hCommHandle;
ADI_SS_RESULT eSSRes;
SS_SMAP_SSN_INFO *pSSnInfo;
ADI_SS_COMM_PROPERTIES pCommProp;
int32_t *pSportIn, *pSportOut,*pSportIn4,*pSportOut4;
adi_initComponents();
if(adi_pwr_audio_config() != 0u)
{
return 1u;
}
/* SPU initialization */
if (Result==0u)
{
Result=SPU_init();
}
/* Switch Configuration */
//Switch_Configurator();
PCG_init();
/* SRU Configuration */
SRU_Init();
/* TWI Initialization */
if (Result==0u)
{
//Result=Init_TWI();
}
/* ADAU1962 Initialization */
if (Result==0u)
{
//Result=ADAU_1962_init();
}
/* ADAU1979 Initialization */
if (Result==0u)
{
//Result=ADAU_1979_init();
}
/*******************************************************************************/
/* SigmaStudio for SHARC (ADSP-SC5xx/ADSP-215xx) library integration */
/* Connection component Initialization */
pConnConfig = &oConnConfig;
pConnConfig->eConnectionType = ADI_SS_CONNECTION_SPI;
pConnConfig->nDevId = 0;
pConnConfig->eProcID = PROCESSOR_SH0;
pConnectionMemBlk = &oConnectionMemBlk;
pConnectionMemBlk->nSize = ADI_SS_CONNECTION_MEMSIZE;
pConnectionMemBlk->pMem = adi_ss_connection_mem;
eConnRet = adi_ss_connection_Init(pConnectionMemBlk, pConnConfig, &hConnHandle);
if(eConnRet != ADI_SS_CONNECTION_SUCCESS)
{
printf("\nConnection component initialization failed");
exit(-1);
}
/* Communication component initialization*/
pCommnConfig = &oCommnConfig;
pCommnConfig->bCRCBypass = false;
pCommnConfig->bFullPacketCRC = true;
pCommnConfig->pfCommCmd4CallBack = (ADI_SS_COMM_CMD4_CB) adi_ss_comm_callback_cmd4;
pCommnConfig->pfCommSMAPCallBack = (ADI_SS_COMM_SMAP_CB) adi_SMAP_Application_Callback;
pCommnConfig->hConnectionHandle = hConnHandle;
pCommnConfig->pMemSMap[PROCESSOR_SH0] = &oSMAPSharc0;
pCommnConfig->pBkChnlInfo[0] = &oBkChannelInfoSharc0;
pCommMemBlk = &oCommMemBlk;
pCommMemBlk->nSize = ADI_SS_COMM_MEMSIZE;
pCommMemBlk->pMem = adi_ss_commn_mem;
eCommRet = adi_ss_comm_Init(pCommMemBlk, pCommnConfig, &hCommHandle);
if(eCommRet != ADI_SS_COMM_SUCCESS)
{
printf("\nCommunication component initialization failed");
exit(-1);
}
/* Wait for SMAP to be received from host */
while(!nSMAPReceived)
{
}
/* Populating Memory addresses of different blocks from SMAP */
oSSnMemMap.nMemBlocks = 11;
pSSnInfo = &oSMAPSharc0.oSSnInfo[0];
for(i=0; i<oSSnMemMap.nMemBlocks; i++)
{
oSSnMemMap.pMemBlocks[i] = &pSSnInfo->oSSnBuff[i];
}
/* Create an instance of SSn */
adi_ss_create( &hSSnHandle, &oSSnMemMap);
if(hSSnHandle == NULL)
{
printf("\n SSn instance creation failed");
exit(-1);
}
/* Provide SSn handle to communication component using the adi_ss_comm_SetProperties() API */
pCommProp.haSSnHandle[PROCESSOR_SH0][0] = hSSnHandle;
pCommProp.nNumProcBlocks = 1;
pCommProp.nProcId = PROCESSOR_SH0;
eCommRet = adi_ss_comm_SetProperties(hCommHandle,ADI_COMM_PROP_SSN_HANDLE,&pCommProp);
if(eCommRet != ADI_SS_COMM_SUCCESS)
{
printf("\nError in Communication component");
exit(-1);
}
/* Initialize the SSn instance */
pSSnConfig = &oSSnConfig;
pSSnConfig->hSSComm = hCommHandle;
pSSnConfig->nBlockSize = BLOCK_SIZE ;
pSSnConfig->nInChannels = 16;
pSSnConfig->nOutChannels = 16;
pSSnConfig->bSkipProcessOnCRCError = 0;
pSSnConfig->bSkipInitialDownload = 0U;
pSSnConfig->nInitNoWait = 0;
pSSnConfig->eProcID = PROCESSOR_SH0;
pSSnConfig->bClearUnusedOutput = 1;
eSSRes = adi_ss_init(hSSnHandle, pSSnConfig);
if(eSSRes != ADI_SS_SUCCESS)
{
printf("\nSSn instance initialization failed");
exit(-1);
}
pSSnProperties = &oSSnProperties;
/* Initialize SigmaStudio I/O pointers */
for(i=0; i<NUM_CHANNELS; i++)
{
pSSInBuff[i] = &aSSInOutBuff[i*BLOCK_SIZE];
pSSOutBuff[i] = pSSInBuff[i];
}
/* Populating hardcoded values for readback */
for(i=0; i<2; i++)
{
oBkChannelInfoSharc0.nAvgMIPS[i]=10.0;
oBkChannelInfoSharc0.nPeakMIPS[i]=20.0;
oBkChannelInfoSharc0.nVersionInfo=0x47000000;
}
/*******************************************************************************/
/* SPORT Initialization */
if (Result==0u)
{
Result=Sport_Init();
}
//if (Result==0u)
//{
//Result=Sport_enable();
//}
/* Close TWI */
if (Result==0u)
{
Result=Stop_TWI();
}
while(1)
{
#ifdef BYPASS_SS
if(nDataAvail >= 1)
{
nDataAvail = 0;
if(CallbackCount == 1)
{
pSportIn = &int_SP0ABuffer4[0];
pSportOut = &int_SP0ABuffer1[0];
}
else if(CallbackCount == 2)
{
pSportIn = &int_SP0ABuffer5[0];
pSportOut = &int_SP0ABuffer2[0];
CallbackCount=0;
}
for(i=0,j=0;i<BLOCK_SIZE*NUM_CHANNELS;i+=NUM_CHANNELS,j+=NUM_CHANNELS)
{
/*Copy ADC buffer to DAC buffer */
pSportOut[j] = pSportIn[i];
pSportOut[j+4] = pSportIn[i];
pSportOut[j+1] = pSportIn[i+1];
pSportOut[j+5] = pSportIn[i+1];
pSportOut[j+2] = pSportIn[i+2];
pSportOut[j+6] = pSportIn[i+2];
pSportOut[j+3] = pSportIn[i+3];
pSportOut[j+7] = pSportIn[i+3];
}
}
#else
if(nDataAvail >= 1)
{
nDataAvail = 0;
if(CallbackCount == 1)
{
pSportIn = &int_SP0ABuffer4[0];
pSportOut = &int_SP0ABuffer1[0];
pSportIn4 = &int_SP0ABuffer8[0];
pSportOut4 = &int_SP0ABuffer6[0];
}
else if(CallbackCount == 2)
{
pSportIn = &int_SP0ABuffer5[0];
pSportOut = &int_SP0ABuffer2[0];
pSportIn4 = &int_SP0ABuffer9[0];
pSportOut4 = &int_SP0ABuffer7[0];
CallbackCount=0;
}
//memcpy(nTempBuff,pSportIn,BLOCK_SIZE*NUM_CHANNELS*sizeof(int));
memcpy(nTempBuff, pSportIn, BLOCK_SIZE * (NUM_CHANNELS/2) * sizeof(int32_t));
memcpy(&nTempBuff[BLOCK_SIZE * (NUM_CHANNELS/2)], pSportIn4, BLOCK_SIZE * (NUM_CHANNELS/2) * sizeof(int32_t));
if(TestCallbackCount == 1000)
{
TestCallbackCount = 1001;
}
/* Fixed to float conversion and copy to SS input buffer */
for(i=0; i<NUM_CHANNELS; i++)
{
//CopyFix2Float((volatile uint32_t*)&pSportIn[i], NUM_CHANNELS, pSSInBuff[i], 1, BLOCK_SIZE, 1u);
CopyFix2Float((volatile uint32_t*)&nTempBuff[i], NUM_CHANNELS, pSSInBuff[i], 1, BLOCK_SIZE, 1u);
}
/* Call to the Schematic processing */
adi_ss_schematic_process(hSSnHandle,BLOCK_SIZE,(adi_ss_sample_t **)pSSInBuff,(adi_ss_sample_t **)pSSOutBuff,pSSnProperties);
/* Float to fix conversion and copy back to SPORT buffer */
for(i=0; i<NUM_CHANNELS/2; i++)
{
CopyFloat2Fix(pSSOutBuff[i], 1, (volatile uint32_t * )&pSportOut[i], NUM_CHANNELS/2, BLOCK_SIZE, 0u);
}
for(i = 0; i < 8; i++) {
// 后8通道：SigmaStudio通道8-15 → SPORT1A
CopyFloat2Fix(pSSOutBuff[i + 8], 1, &pSportOut4[i], 8, BLOCK_SIZE, 0u);
}
#if 0
/* Overwrite */
for(i=0,j=0;i<BLOCK_SIZE*NUM_CHANNELS;i+=NUM_CHANNELS,j+=NUM_CHANNELS)
{
/*Copy ADC buffer to DAC buffer */
pSportOut[j] = pSportIn[i];
pSportOut[j+4] = 0;
pSportOut[j+1] = pSportIn[i+1];
pSportOut[j+5] = 0;
pSportOut[j+2] = 0;
pSportOut[j+6] = 0;
pSportOut[j+3] = 0;
pSportOut[j+7] = 0;
}
#endif
if(nDataAvail >= 1)
{
printf("\n Input buffer overflow detected");
exit(-1);
}
}
#endif
}
}
void adi_SMAP_Application_Callback(ADI_SS_PROC_ID eCoreID)
{
if(eCoreID==PROCESSOR_SH0)
{
nSMAPReceived = 1;
}
}
void adi_ss_comm_callback_cmd4(uint32_t *pCommPayloadBuff, int32_t nPayloadCount, ADI_SS_SSN_HANDLE hSSn)
{
;
}
