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Configuring clocks on ADSP-21565

Category: Hardware
Product Number: ADSP-21565

Hello,

I work on a custom board with an ADSP-21565.

I am searching for information regarding clock configuration (SYSCLK, CCLK, and SCLK). How to chose frequencies (tradeoffs?) and how to configure them.

For example I read on this forum that by default SCLK is 93.75MHz, and it seems to be the case with my experimentations. Is there an official information about this?

I work on an audio product with DACs, ADCs and need to implement I2S and TDM communications. Audio will be running at 48kH. I have a separate clock coming into the DSP from a DAI for driving audio communications (DACs receive the same), so I am not sure the DSP clocks are so relevant to me. Could you provide guidance regarding those subjects?

My project will integrate SigmaStudio.

Thanks a lot,

Fabien

Parents Reply
  • Hi,

    Since you're working with a custom board, some experimentation will be necessary to tailor configurations such as ADC, DAC, DSP clocks, and SPORT interfaces to your specific setup. The examples we've provided are intended for reference and are based on Analog Devices' standard evaluation boards, which may not cover all customer-specific use cases.

    Regarding the Init .dxe file, it's primarily used to configure core clocks and memory for evaluation boards. You can refer to the init application code available in the CCES installation directory. This code will need to be adapted to suit your custom platform, based on your hardware design.


    "C:\analog\cces\3.0.2\SHARC\ldr\init_code\2156x_Init"

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