what's the relation between the sports used in the framework and sports using in Sigmastudio plus ?

Hi Eliam,

The SPORT configuration from the SS+ UI, in a way, can be said to be primarily intended for "Demo" applications included with the SS+ installation package.

The reason we highlight this is because, unlike the Demo application, if we look at the LibIntegrationExample for the ADSP-21569 (or any other processor), we can notice that SPORT configurations are handled directly within the target application rather than through the UI. As you mentioned, by reviewing the Sport_Init() function, we can see that SPORTs 4A and 4B are used for data transmission (Tx) and reception (Rx). Similarly, in the SRU_Init() function, we can observe the relevant DAI pin routing being configured to connect the ADC/DAC with the corresponding SPORTs.

To answer your question: if you want to change the SPORTs used for Tx/Rx or modify the associated DAI pins, you will need to make the appropriate changes in both the Sport_Init() and SRU_Init() functions, rather than from the UI alone.

hi VSankar

thanks for clarifying!

I have run lots of example , but all the examples only have one sport for receive and one for transmit ,  is there example use multi sports than two(, I want to take ref how the DMA  and buffer is design in the target application , and how to handle two inputs and outputs in SS+ .

as you can see, we have one tdm16 for playing audio , and one tdm16 for recording (need 4 sports ), how to add two sports in the target application to make the aplaying and recording independent and non-block? can I just add the other sports open and configurations in the Sport_Init() function and SRU_Init() function like 4A and 4B? 

Hi Eliam,

Yes. To include multiple SPORTs for input/output in LibIntegration, as you mentioned, you just need to follow the same configuration pattern used for SPORTs 4A and 4B.

Apart from that, you have to change the number of input and output channels from the default of 8 to the desired numbers in the main() function.

We also hope you will take care of the memcpy operations for multiple SPORT data before and after the schematic processing inside the main while loop.

hi VSankar

when I declare multiple sports , for example , add sport 0A  0B for another tdm16 transmit, how should I trigger the data processing in while loop,

the 4A and  4B use variable nDataAvail and CallbackCount to imply when and which sport buffer, should I use the same variable or declare the other counter variable , and add another if(nDataAvail2 >=1)  ?

can you provide a prototype for this?

Hi Eliam,

No need to add separate variables. You can include the SPORT buffers along with the buffers for SPORT 4A and 4B.

Primarily, you need to modify the contents of the SPU_init, SRU_Init, Sport_Init functions.

In the main while loop, you can do something like the example shown below (using sample SPORTs like 5A, 5B, etc.):

if(CallbackCount == 1)
{
pSportIn1 = &int_SP0ABuffer3[0]; //4B
pSportOut1 = &int_SP0ABuffer1[0]; //4A

/**********Other Sport buffer handlings**********/
pSportIn2 = &int_SP0ABuffer7[0]; //5B
pSportOut2 = &int_SP0ABuffer5[0]; //5A
pSportIn3 = &int_SP0ABuffer11[0]; //6B
pSportOut3 = &int_SP0ABuffer9[0]; //6A
/****************************************************/
}
else if(CallbackCount == 2)
{
pSportIn1 = &int_SP0ABuffer4[0]; //4B
pSportOut1 = &int_SP0ABuffer2[0]; //4A

/**********Other Sport buffer handlings**********/
pSportIn2 = &int_SP0ABuffer8[0]; //5B
pSportOut2 = &int_SP0ABuffer6[0]; //5A
pSportIn3 = &int_SP0ABuffer12[0]; //6B
pSportOut3 = &int_SP0ABuffer10[0]; //6A
/****************************************************/

CallbackCount=0;
}

Similarly, the memcpy, CopyFix2Float and CopyFloat2Fix functions after this should also be updated to handle data from multiple SPORTs.

hi VSankar

thanks for your reply!

I didn't get this "You can include the SPORT buffers along with the buffers for SPORT 4A and 4B",  the  CallbackCount counter is register for sport 4B,  how to make it update for other receive sport like 5B?

eResult = adi_sport_RegisterCallback(hSPORTDev4BRx,SPORTCallback,NULL);

Hi Eliam,

If we check the code shared in the previous reply, we can see that for each SPORT callback for SPORT 4B (since, as you mentioned, only a callback is registered for SPORT 4B), we are copying buffer data not only from SPORT 4B but also from all the other SPORT buffers at the same time. So, with a single callback, all SPORT buffer data can be handled, rather than complicating the code with multiple callback handlers.

hi VSankar

I have write a example code below, can you help me check if there is any issues in the buffer ,memory copy or other issues?  the code init 3 sports , 0B for receive(TDM16 BCLK:24.576M  FRAME SYNC: 48K  32BIT) , 4A for transmit (BCLK:24.576M  FRAME SYNC: 48K  32BIT) ,5A for another transmit of the data receive by sport 0B in tdm8 (BCLK:12.288M  FRAME SYNC: 48K  32BIT).

/*****************************************************************************
Copyright (c) 2019-2023 Analog Devices Inc. All rights reserved
This software is proprietary & confidential to Analog Devices, Inc.
and its licensors.
*****************************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <sys/platform.h>
#include <sys/adi_core.h>
#include "adi_initialize.h"
#include <services/int/adi_int.h>
#include <drivers/sport/adi_sport.h>
#include <services/spu/adi_spu.h>
#include <drivers/twi/adi_twi_2156x.h>
#include "ADAU_1962Common.h"
#include "ADAU_1979Common.h"
#include <cdef21569.h>
#include "math.h"
#include <string.h>
#include <sru21569.h>
#include "LibIntegrationExample_Core1.h"
#include "adi_ss_smap.h"
#include "adi_ss_ssn_export_export_DiffDXESchematic_IC_1.h"
#include "adi_ss_utility.h"
#include <services/pcg/adi_pcg.h>

#ifdef DO_CYCLE_COUNTS
#include "cycles.h"
#endif

/******* SigmaStudio Integration ***************/

#define ADI_SS_APP_DELAY_100_MSEC (100 * 10000)
/*Defining Backchannel info structure. Will be populated by the framework */
typedef struct ADI_SS_BACKCH_INFO
{
    float32_t    nPeakMIPS[ADI_SS_FW_MAX_PROC_BLOCKS]; /*!< Peak MIPS for all process blocks */
    float32_t    nAvgMIPS[ADI_SS_FW_MAX_PROC_BLOCKS];  /*!< Average MIPS for all process blocks */
    uint32_t     nVersionInfo;                  	   /*!< Target library API version */
    uint32_t     nSSnDownloadStatus;            	   /*!< Current download status of SSns within all process blocks*/
}ADI_SS_BACKCH_INFO;

#include "adi_ss_connection.h"
#include "adi_ss_communication.h"
#include "adi_ss_ssn.h"

/* Memory for SigmaStudio for Griffin libraries */
/* Connection and Communication Instance Mem */
#pragma align(4)
#pragma section("ss_app_data0_fast")
uint8_t adi_ss_commn_mem[ADI_SS_COMM_MEMSIZE];
#pragma align(4)
#pragma section("ss_app_data0_fast")
uint8_t adi_ss_connection_mem[ADI_SS_CONNECTION_MEMSIZE];

bool bSportCallback;
volatile uint32_t nSMAPReceived=0;

/* SMAP */
ADI_SS_MEM_SMAP oSMAPSharc0;
ADI_SS_MEM_MAP oSSnMemMap;

/* SSn Config structure */
ADI_SS_CONFIG  *pSSnConfig,oSSnConfig;

/* SSnProperties structure */
ADI_SS_SSNPROPERTIES *pSSnProperties,oSSnProperties;

/* Defining SSn Handle */
ADI_SS_SSN_HANDLE hSSnHandle;

/* Backchannel info */
ADI_SS_BACKCH_INFO 	oBkChannelInfoSharc0;

/* I/O buffer and pointers for SSn instance */
float32_t aSSInOutBuff[BLOCK_SIZE*(NUM_CHANNELS+NUM_CHANNELS2)];
float32_t *pSSInBuff[NUM_CHANNELS+NUM_CHANNELS2];
float32_t *pSSOutBuff[NUM_CHANNELS+NUM_CHANNELS2];

void adi_ss_comm_callback_cmd4(uint32_t  *pCommPayloadBuff,
                               int32_t   nPayloadCount,
                               ADI_SS_SSN_HANDLE hSSn);

void adi_SMAP_Application_Callback(ADI_SS_PROC_ID eCoreID);

/* Convert the audio samples generated by ADC into float format */
void    CopyFix2Float( volatile        uint32_t  *pInBuffer,
                                        uint32_t nInStride,
                       volatile        float    *pOutBuffer,
                                        uint32_t nOutStride,
                                        uint32_t nBlockSize,
                                        uint32_t nShiftFlag);

/* Convert the audio samples from float to fixed point (which can be consumed by DAC) */
uint32_t CopyFloat2Fix(volatile   float *pInBuffer,
                                        uint32_t nInStride,
                               volatile uint32_t *pOutBuffer,
                                        uint32_t nOutStride,
                                        uint32_t nBlockSize,
                                        uint32_t nShiftFlag);

/******* SigmaStudio Integration END  ***************/


/* SPORT buffers */
int32_t int_SP0ABuffer1[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer2[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer4[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer5[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer6[BLOCK_SIZE*NUM_CHANNELS2];
int32_t int_SP0ABuffer7[BLOCK_SIZE*NUM_CHANNELS2];

struct Config_Table
{
	short Reg_Add;
	char  Value;
};

char Config_read_DAC[28];
char Config_read_ADC[16];

/* Dev buffer for configuring ADC-DAC through TWI*/
static uint8_t devBuffer[BUFFER_SIZE];

extern void ConfigSoftSwitches_ADC_DAC(void);

extern void ConfigSoftSwitches_ADAU_Reset(void);

#if 0
struct Config_Table Config_array_DAC[28] = {
		   	    {     ADAU1962_PDN_CTRL_1,		0x00},
		   	    {     ADAU1962_PDN_CTRL_2,	    0xff},
		   	    {     ADAU1962_PDN_CTRL_3,	    0x0f},
		   	    {     ADAU1962_DAC_CTRL0,		0x01},
		   	    {     ADAU1962_DAC_CTRL1,		0x41},
		   	    {     ADAU1962_DAC_CTRL2,		0x00},
		   	    {     ADAU1962_DAC_MUTE1,	    0x0},
		   	    {     ADAU1962_DAC_MUTE2,	    0x00},
		   	    {     ADAU1962_MSTR_VOL,		0x00},
			    {     ADAU1962_DAC1_VOL,	    0x00},
			    {     ADAU1962_DAC2_VOL,		0x00},
				{     ADAU1962_DAC3_VOL,		0x00},
				{     ADAU1962_DAC4_VOL,		0x00},
				{     ADAU1962_DAC5_VOL,		0x00},
				{     ADAU1962_DAC6_VOL,		0x00},
				{     ADAU1962_DAC7_VOL,		0x00},
				{     ADAU1962_DAC8_VOL,	    0x00},
				{     ADAU1962_DAC9_VOL,		0x00},
				{     ADAU1962_DAC10_VOL,		0x00},
				{     ADAU1962_DAC11_VOL,		0x00},
				{     ADAU1962_DAC12_VOL,		0x00},
				{     ADAU1962_PAD_STRGTH,		0x00},
				{     ADAU1962_DAC_PWR1,		0xaa},
				{     ADAU1962_DAC_PWR2,		0xaa},
				{     ADAU1962_DAC_PWR3,		0xaa},
				{     ADAU1962_PDN_CTRL_2,	    0x00},
				{     ADAU1962_PDN_CTRL_3,	    0x00},
				{     ADAU1962_DAC_CTRL0,		0x18}

};
#else
struct Config_Table Config_array_DAC[28] = {
		   	    {     ADAU1962_PDN_CTRL_1,		0xa4 },
		   	    {     ADAU1962_PDN_CTRL_2,	    0xff },  //Power down DAC
		   	    {     ADAU1962_PDN_CTRL_3,	    0x0f }, //Power down DAC
		   	    {     ADAU1962_DAC_CTRL0,		0x19 },
		   	    {     ADAU1962_DAC_CTRL1,		0x63 }, // pulse mode LRCLK, MSB first //orginal value =42
		   	    {     ADAU1962_DAC_CTRL2,		0x04 },  // TDM Configuration
		   	    {     ADAU1962_DAC_MUTE1,	    0x00 },
		   	    {     ADAU1962_DAC_MUTE2,	    0x00 },
		   	    {     ADAU1962_MSTR_VOL,		0x00 },
			    {     ADAU1962_DAC1_VOL,	    0x00 } ,
			    {     ADAU1962_DAC2_VOL,		0x00 },
				{     ADAU1962_DAC3_VOL,		0x00 },
				{     ADAU1962_DAC4_VOL,		0x00 },
				{     ADAU1962_DAC5_VOL,		0x00 },
				{     ADAU1962_DAC6_VOL,		0x00 },
				{     ADAU1962_DAC7_VOL,		0x00 },
				{     ADAU1962_DAC8_VOL,	    0x00 },
				{     ADAU1962_DAC9_VOL,		0x00 },
				{     ADAU1962_DAC10_VOL,		0x00 },
				{     ADAU1962_DAC11_VOL,		0x00 },
				{     ADAU1962_DAC12_VOL,		0x00 },
				{     ADAU1962_PAD_STRGTH,		0x00 },
				{     ADAU1962_DAC_PWR1,		0xaa },
				{     ADAU1962_DAC_PWR2,		0xaa },
				{     ADAU1962_DAC_PWR3,		0xaa },
				{     ADAU1962_PDN_CTRL_2,	    0x00 },
				{     ADAU1962_PDN_CTRL_3,	    0x00 },
		   	    {     ADAU1962_DAC_CTRL0,		0x18 },
};
#endif

#if 0
struct Config_Table Config_array_ADC[16] = {

		 {ADAU1979_REG_BOOST			,	0x00},
		 {ADAU1979_REG_MICBIAS			,	0x00},
		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0x30},
		 /*{ADAU1979_REG_SAI_CTRL0		,	0x1B}, */
		 {ADAU1979_REG_SAI_CTRL0		,	0x1A},/*I2S format*/
		 {ADAU1979_REG_SAI_CTRL1		,	0x08},
		 {ADAU1979_REG_CMAP12			,	0x10},
		 {ADAU1979_REG_CMAP34			,	0x32},
		 {ADAU1979_REG_SAI_OVERTEMP		,	0xf0},
		 {ADAU1979_REG_POST_ADC_GAIN1 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN2 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN3 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN4 	,	0xA0},
		 {ADAU1979_REG_ADC_CLIP			,	0x00},
		 {ADAU1979_REG_DC_HPF_CAL		,	0x00},
		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0x3f},
		 {ADAU1979_REG_MISC_CONTROL		,	0x02}
};
#else
struct Config_Table Config_array_ADC[16] = {

		 {ADAU1979_REG_BOOST			,	0x00},
		 {ADAU1979_REG_MICBIAS			,	0x00},
 		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0xb0},//power down ADC LDO enabel
		 {ADAU1979_REG_SAI_CTRL0		,	0x5a},//TDM 48kHz
		 {ADAU1979_REG_SAI_CTRL1		,	0x08},//LRCLK pulse mode //original value =08
		 {ADAU1979_REG_CMAP12			,	0x10},
		 {ADAU1979_REG_CMAP34			,	0x32},
		 {ADAU1979_REG_SAI_OVERTEMP		,	0xf0},
		 {ADAU1979_REG_POST_ADC_GAIN1 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN1 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN3 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN4 	,	0xA0},
		 {ADAU1979_REG_ADC_CLIP			,	0x00},
		 {ADAU1979_REG_DC_HPF_CAL		,	0x00},// filter off
		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0xbf},//power on  ADC LDO enable
		 {ADAU1979_REG_MISC_CONTROL		,	0x02},//mute all channels
};
#endif

/* Destination PDMA lists */
ADI_PDMA_DESC_LIST iDESC_LIST_1_SP4A;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP4A ;

/* Source PDMA lists */
ADI_PDMA_DESC_LIST iSRC_LIST_1_SP0B ;
ADI_PDMA_DESC_LIST iSRC_LIST_2_SP0B ;

/* Destination PDMA lists */
ADI_PDMA_DESC_LIST iDESC_LIST_1_SP5A;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP5A ;

/* Prepares descriptors for SPORT DMA */
static void PrepareDescriptors (void);

/* Count to track the number of callBacks for SPORT transfer */
volatile uint8_t CallbackCount = 0;
volatile uint32_t TestCallbackCount = 0;
volatile uint32_t nDataAvail=0;


/* Memory required for SPORT */
static uint8_t SPORTMemory4A[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory0B[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory5A[ADI_SPORT_MEMORY_SIZE];

/* SPORT Handle */
static ADI_SPORT_HANDLE hSPORTDev4ATx;//TX
static ADI_SPORT_HANDLE hSPORTDev0BRx;//RX
static ADI_SPORT_HANDLE hSPORTDev5ATx;//TX

/* Memory required for TWI */
uint8_t TwideviceMemory[ADI_TWI_MEMORY_SIZE];

/* TWI driver handle */
static ADI_TWI_HANDLE hTwiDevice;

/* SPU handle */
static ADI_SPU_HANDLE      ghSpu;

/* Memory required for the SPU operation */
uint8_t             SpuMemory[ADI_SPU_MEMORY_SIZE];

int32_t delay;

static int32_t ADAU_1962_Pllinit(void);
static int32_t ADAU_1979_Pllinit(void);
void Switch_Configurator(void);
static int32_t ADAU_1962_init(void);
static int32_t ADAU_1979_init(void);
void SRU_Init(void);
static int32_t Sport_Init(void);
static int32_t Sport_Stop(void);
static int32_t SPU_init(void);
static void PrepareDescriptors (void);
static int32_t Init_TWI(void);
static int32_t Stop_TWI(void);
static void PCG_init(void);

static void PCG_init(void)
{

	ADI_PCG_CLK_INFO gClkInfoC;
			gClkInfoC.eClkInput = ADI_PCG_CLK_CLKIN0;               /* Clock Source */
			gClkInfoC.nDiv = 1;                 /* Clock Divisor */
			gClkInfoC.bExternalTrigger = false;                    /* External Trigger */


	ADI_PCG_FS_INFO gFsInfoC;
			gFsInfoC.eClkInput = ADI_PCG_FS_CLKIN0;                               /* Clock Source */
			gFsInfoC.nDiv = (gClkInfoC.nDiv)*(ADI_SPORT0A_CTL_SLEN + 1)*(NUM_CHANNELS);     /* Frame Sync Divisor */
			gFsInfoC.nPulseWidth = 1;                            /* Pulse Width */
			gFsInfoC.nPhase = 2;                                /* Phase */
			gFsInfoC.bExternalTrigger = false;                                   /* External Trigger */
			gFsInfoC.eFsBypassMode = ADI_PCG_FSBYPASS_MODE_NORMAL;               /* Bypass Mode */

			adi_pcg_Init(ADI_PCG_DEV_C,&gClkInfoC,&gFsInfoC);

	ADI_PCG_CLK_INFO gClkInfoD;
				gClkInfoD.eClkInput = ADI_PCG_CLK_CLKIN0;               /* Clock Source */
				gClkInfoD.nDiv = 2;                 /* Clock Divisor */
				gClkInfoD.bExternalTrigger = false;                    /* External Trigger */


	ADI_PCG_FS_INFO gFsInfoD;
			gFsInfoD.eClkInput = ADI_PCG_FS_CLKIN0;                               /* Clock Source */
			gFsInfoD.nDiv = (gClkInfoD.nDiv)*(ADI_SPORT5A_CTL_SLEN + 1)*(NUM_CHANNELS2);     /* Frame Sync Divisor */
			gFsInfoD.nPulseWidth = 1;                            /* Pulse Width */
			gFsInfoD.nPhase = 2;                                /* Phase */
			gFsInfoD.bExternalTrigger = false;                                   /* External Trigger */
			gFsInfoD.eFsBypassMode = ADI_PCG_FSBYPASS_MODE_NORMAL;               /* Bypass Mode */

			adi_pcg_Init(ADI_PCG_DEV_D,&gClkInfoD,&gFsInfoD);



}
static void SPORTCallback(void        *pAppHandle,
						  uint32_t     nEvent,
						  void        *pArg
						 )
{
	int32_t i;
	int32_t j;

	ADI_SPORT_RESULT eResult;
    /* CASEOF (event type) */
    switch (nEvent)
    {
        /* CASE (buffer processed) */
        case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
        		TestCallbackCount += 1;
        		CallbackCount += 1;
        		nDataAvail += 1;
        		break;
        default:
        	 break;
    }
    /* return */
}

/*
 * Prepares descriptors for Memory DMA copy.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */

static void PrepareDescriptors (void)
{

	iDESC_LIST_1_SP4A.pStartAddr	= (int32_t *)int_SP0ABuffer1;
	iDESC_LIST_1_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_1_SP4A.XCount		= BLOCK_SIZE*NUM_CHANNELS;
	iDESC_LIST_1_SP4A.XModify		= 4;
	iDESC_LIST_1_SP4A.YCount		= 0;
	iDESC_LIST_1_SP4A.YModify		= 0;
	iDESC_LIST_1_SP4A.pNxtDscp		= &iDESC_LIST_2_SP4A;

	iDESC_LIST_2_SP4A.pStartAddr	= (int32_t *)int_SP0ABuffer2;
	iDESC_LIST_2_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_2_SP4A.XCount		= BLOCK_SIZE*NUM_CHANNELS;
	iDESC_LIST_2_SP4A.XModify		= 4;
	iDESC_LIST_2_SP4A.YCount		= 0;
	iDESC_LIST_2_SP4A.YModify		= 0;
	iDESC_LIST_2_SP4A.pNxtDscp		= &iDESC_LIST_1_SP4A;

	iSRC_LIST_1_SP0B.pStartAddr		=(int32_t *)int_SP0ABuffer4;
	iSRC_LIST_1_SP0B.Config			= ENUM_DMA_CFG_XCNT_INT ;
	iSRC_LIST_1_SP0B.XCount			= BLOCK_SIZE*NUM_CHANNELS;
	iSRC_LIST_1_SP0B.XModify		= 4;
	iSRC_LIST_1_SP0B.YCount			= 0;
	iSRC_LIST_1_SP0B.YModify		= 0;
	iSRC_LIST_1_SP0B.pNxtDscp		= &iSRC_LIST_2_SP0B;

	iSRC_LIST_2_SP0B.pStartAddr		=(int32_t *)int_SP0ABuffer5;
	iSRC_LIST_2_SP0B.Config			= ENUM_DMA_CFG_XCNT_INT;
	iSRC_LIST_2_SP0B.XCount			= BLOCK_SIZE*NUM_CHANNELS;
	iSRC_LIST_2_SP0B.XModify		= 4;
	iSRC_LIST_2_SP0B.YCount			= 0;
	iSRC_LIST_2_SP0B.YModify		= 0;
	iSRC_LIST_2_SP0B.pNxtDscp		= &iSRC_LIST_1_SP0B;

	iDESC_LIST_1_SP5A.pStartAddr	= (int32_t *)int_SP0ABuffer6;
	iDESC_LIST_1_SP5A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_1_SP5A.XCount		= BLOCK_SIZE*NUM_CHANNELS2;
	iDESC_LIST_1_SP5A.XModify		= 4;
	iDESC_LIST_1_SP5A.YCount		= 0;
	iDESC_LIST_1_SP5A.YModify		= 0;
	iDESC_LIST_1_SP5A.pNxtDscp		= &iDESC_LIST_2_SP5A;

	iDESC_LIST_2_SP5A.pStartAddr	= (int32_t *)int_SP0ABuffer7;
	iDESC_LIST_2_SP5A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_2_SP5A.XCount		= BLOCK_SIZE*NUM_CHANNELS2;
	iDESC_LIST_2_SP5A.XModify		= 4;
	iDESC_LIST_2_SP5A.YCount		= 0;
	iDESC_LIST_2_SP5A.YModify		= 0;
	iDESC_LIST_2_SP5A.pNxtDscp		= &iDESC_LIST_1_SP5A;


}

static int32_t Sport_Init()
{
    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

	/* Open the SPORT Device 4A */
	eResult = adi_sport_Open(SPORT_DEVICE_4A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_MC_MODE, SPORTMemory4A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/* Open the SPORT Device 0B*/
	eResult = adi_sport_Open(SPORT_DEVICE_0B,ADI_HALF_SPORT_B,ADI_SPORT_DIR_RX, ADI_SPORT_MC_MODE, SPORTMemory0B,ADI_SPORT_MEMORY_SIZE,&hSPORTDev0BRx);
	CHECK_RESULT(eResult);
	/* Open the SPORT Device 4A */
	eResult = adi_sport_Open(SPORT_DEVICE_5A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_MC_MODE, SPORTMemory5A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev5ATx);
	CHECK_RESULT(eResult);


	/* Configure the data,clock,frame sync and MCTL of SPORT Device 4A*/
	eResult = adi_sport_ConfigData(hSPORTDev4ATx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigClock(hSPORTDev4ATx,32,false,/*false*/ true,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigFrameSync(hSPORTDev4ATx,31,false,false,true,/*true*/ false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigMC(hSPORTDev4ATx,0u,15u,0u,true);
	CHECK_RESULT(eResult);
	eResult = adi_sport_SelectChannel(hSPORTDev4ATx,0u,15u);
	CHECK_RESULT(eResult);

	/* Configure the data,clock,frame sync and MCTL of SPORT Device 0B*/
	eResult = adi_sport_ConfigData(hSPORTDev0BRx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigClock(hSPORTDev0BRx,32,false,/*false*/ false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigFrameSync(hSPORTDev0BRx,31,false,false,true,/*true*/ true,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigMC(hSPORTDev0BRx,0u,15u,0u,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_SelectChannel(hSPORTDev0BRx,0u,15u);
	CHECK_RESULT(eResult);

	/* Configure the data,clock,frame sync and MCTL of SPORT Device 5A*/
	eResult = adi_sport_ConfigData(hSPORTDev5ATx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigClock(hSPORTDev5ATx,32,false,/*false*/ true,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigFrameSync(hSPORTDev5ATx,31,false,false,true,/*true*/ false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigMC(hSPORTDev5ATx,0u,7u,0u,true);
	CHECK_RESULT(eResult);
	eResult = adi_sport_SelectChannel(hSPORTDev5ATx,0u,7u);
	CHECK_RESULT(eResult);

	/* Register SPORT Callback function */
	eResult = adi_sport_RegisterCallback(hSPORTDev0BRx,SPORTCallback,NULL);
	CHECK_RESULT(eResult);

	/* Prepare descriptors */
	PrepareDescriptors();

	/* Submit the first buffer for Rx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev0BRx,&iSRC_LIST_1_SP0B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);
	/* Submit the first buffer for Tx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev4ATx,&iDESC_LIST_1_SP4A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);

	/* Submit the first buffer for Tx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev5ATx,&iDESC_LIST_1_SP5A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);

	/*Enable the Sport Device 0B */
	eResult = adi_sport_Enable(hSPORTDev0BRx,true);
	CHECK_RESULT(eResult);
	/*Enable the Sport Device 4A */
	eResult = adi_sport_Enable(hSPORTDev4ATx,true);
	CHECK_RESULT(eResult);
	/*Enable the Sport Device 5A */
	eResult = adi_sport_Enable(hSPORTDev5ATx,true);
	CHECK_RESULT(eResult);

	return eResult;

}

static int32_t Sport_Stop(void)
{
    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

    /*Stop the DMA transfer of  Sport Device 0B */
	eResult = adi_sport_StopDMATransfer(hSPORTDev0BRx);
	CHECK_RESULT(eResult);
	/*Stop the DMA transfer of  Sport Device 4A */
	eResult = adi_sport_StopDMATransfer(hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/*Stop the DMA transfer of  Sport Device 5A */
	eResult = adi_sport_StopDMATransfer(hSPORTDev5ATx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 0B */
	eResult = adi_sport_Close(hSPORTDev0BRx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 4A */
	eResult = adi_sport_Close(hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 5A */
	eResult = adi_sport_Close(hSPORTDev5ATx);
	CHECK_RESULT(eResult);

	return eResult;
}

/*
 * Prepares Switch configuration.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */
void Switch_Configurator()
{
	int32_t delay11=0xffff;


	/* Software Switch Configuration for Re-Setting ADC-DAC  */
	ConfigSoftSwitches_ADAU_Reset();

	while(delay11--)
	{
		asm("nop;");
	}

	/* Software Switch Configuration for Enabling ADC-DAC */
	ConfigSoftSwitches_ADC_DAC();

	/* wait for Codec to up */
	delay11=0xffff;
	while(delay11--)
	{
		asm("nop;");
	}
}



/*
 * Prepares SRU configuration.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */
void SRU_Init()
{
	*pREG_PADS0_DAI0_IE=0xfffff;
	*pREG_PADS0_DAI1_IE=0xfffff;

	// SPORT 0B configuration
	SRU(LOW,DAI0_PBEN05_I);
	SRU(DAI0_PB05_O,SPT0_BD0_I);
	SRU(LOW,DAI0_PBEN07_I);
	SRU(DAI0_PB07_O,SPT0_BCLK_I);
	SRU(LOW,DAI0_PBEN08_I);
	SRU(DAI0_PB08_O,SPT0_BFS_I);

	// SPORT 4A configuration
	SRU2(HIGH,DAI1_PBEN01_I);
	SRU2(SPT4_AD0_O,DAI1_PB01_I);

	SRU2(HIGH,DAI1_PBEN03_I);
	SRU2(PCG0_CLKC_O,DAI1_PB03_I);
	SRU2(PCG0_FSC_O,DAI1_PB04_I);
	SRU2(HIGH,DAI1_PBEN04_I);

	SRU2(PCG0_CLKC_O,SPT4_ACLK_I);
	SRU2(PCG0_FSC_O,SPT4_AFS_I);

	// SPORT 5A configuration
	SRU2(HIGH,DAI1_PBEN10_I);
	SRU2(SPT5_AD0_O,DAI1_PB10_I);

	SRU2(HIGH,DAI1_PBEN20_I);
	SRU2(PCG0_CLKD_O,DAI1_PB20_I);
	SRU2(HIGH,DAI1_PBEN11_I);
	SRU2(PCG0_CLKD_O,DAI1_PB11_I);
	SRU2(PCG0_FSD_O,DAI1_PB12_I);
	SRU2(HIGH,DAI1_PBEN12_I);

	SRU2(PCG0_CLKD_O,SPT5_ACLK_I);
	SRU2(PCG0_FSD_O,SPT5_AFS_I);

	/*SRU2(HIGH,DAI1_PBEN03_I);
	SRU2(DAI1_CRS_PB03_O,DAI1_PB03_I);
	SRU2(DAI1_CRS_PB04_O,DAI1_PB04_I);
	SRU2(HIGH,DAI1_PBEN04_I);

	SRU2(DAI1_CRS_PB03_O,SPT4_ACLK_I);
	SRU2(DAI1_CRS_PB04_O,SPT4_AFS_I);*/

}

/*
 * Prepares SPU configuration.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */
int32_t SPU_init(void)
{
    if(adi_spu_Init(0, SpuMemory, NULL, NULL, &ghSpu) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to initialize SPU service\n");
		return FAILED;
    }

    /* Make SPORT 0A to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_4A_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT4A\n");
		return FAILED;
    }
    /* Make SPORT 0A to generate secure transactions */
       if(adi_spu_EnableMasterSecure(ghSpu, SPORT_5A_SPU, true) != ADI_SPU_SUCCESS)
       {
       	REPORT_ERROR("Failed to enable Master secure for SPORT5A\n");
   		return FAILED;
       }
    /* Make SPORT 0B to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_0B_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT0B\n");
		return FAILED;
    }

    return SUCCESS;
}

void Write_TWI_8bit_Reg(unsigned char Reg_ID, unsigned char Tx_Data)
{
	devBuffer[0] = Reg_ID;
	devBuffer[1] = Tx_Data;
	adi_twi_Write(hTwiDevice, devBuffer, 2u, false);
}

uint8_t Read_TWI_8bit_Reg(unsigned char Reg_ID)
{
	ADI_TWI_RESULT eResult;
	uint8_t Rx_Data;

	/* write register address */
	devBuffer[0] = Reg_ID;
	eResult = adi_twi_Write(hTwiDevice, devBuffer, 1u, true);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI write failed 0x%08X\n", eResult);
	}

	/* read register value */
	eResult = adi_twi_Read(hTwiDevice, &Rx_Data, 1u, false);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Read failed 0x%08X\n", eResult);
	}

	return Rx_Data;
}

static int32_t Init_TWI(void)
{
	ADI_TWI_RESULT eResult;

	eResult = adi_twi_Open(TWIDEVNUM, ADI_TWI_MASTER, &TwideviceMemory[0],
			   	ADI_TWI_MEMORY_SIZE, &hTwiDevice);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Open failed 0x%08X\n", eResult);
	}

	eResult = adi_twi_SetPrescale(hTwiDevice, PRESCALEVALUE);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Prescale failed 0x%08X\n", eResult);
	}

	eResult = adi_twi_SetBitRate(hTwiDevice, BITRATE);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Bitrate failed 0x%08X\n", eResult);
	}


	eResult = adi_twi_SetDutyCycle(hTwiDevice, DUTYCYCLE);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Duty cycle failed 0x%08X\n", eResult);
	}

	eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
	}

	return eResult;
}

static int32_t Stop_TWI(void)
{
	ADI_TWI_RESULT eResult;

	eResult = adi_twi_Close(hTwiDevice);
	CHECK_RESULT(eResult);

	return eResult;
}

/*****************************************************************************************************************************/

static int32_t ADAU_1962_init(void)
{
	int32_t i;
	ADAU_1962_Pllinit();
	for(i=0;i<28;i++)
	{
		/* write value */
		Write_TWI_8bit_Reg(Config_array_DAC[i].Reg_Add,Config_array_DAC[i].Value);
		Config_read_DAC[i]=Read_TWI_8bit_Reg(Config_array_DAC[i].Reg_Add);
		if(Config_array_DAC[i].Value!= Config_read_DAC[i])
		{
			DEBUG_INFORMATION("\n Configuring ADAU_1962 failed");
			return FAILED;
		}
	}

	return SUCCESS;
}

static int32_t ADAU_1962_Pllinit(void)
{
	int32_t status,delay1=0xffff;

	ADI_TWI_RESULT eResult;

   	eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR_1962);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
	}

	Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x01);
	while(delay1--)
	{
		asm("nop;");
	}

	Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x05);

	delay1=0xffff;
	while(delay1--)
	{
		asm("nop;");
	}

	Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1,0x22);
	delay1=0xffff;
	while(delay1--)
	{
		asm("nop;");
	}
	status=Read_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1);
	while(!((status & 0x4)>>2)  )
	{
		status=Read_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1);
	}

	return eResult;
}




static int32_t ADAU_1979_init(void)
{
	int32_t i;

	ADAU_1979_Pllinit();

	for(i=0; i<16; i++)
	{
		Write_TWI_8bit_Reg(Config_array_ADC[i].Reg_Add,Config_array_ADC[i].Value);
		Config_read_ADC[i]=Read_TWI_8bit_Reg(Config_array_ADC[i].Reg_Add);
		if(Config_array_ADC[i].Value!= Config_read_ADC[i])
		{
			DEBUG_INFORMATION("\n Configuring ADAU_1979 failed");
			return FAILED;
		}
	}

	return SUCCESS;
}

static int32_t ADAU_1979_Pllinit(void)
{

	int32_t status,delay1=0xffff;

	ADI_TWI_RESULT eResult;

   	eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR_1979);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
	}

   	Write_TWI_8bit_Reg(ADAU1979_REG_POWER,0x01);
	Write_TWI_8bit_Reg(ADAU1979_REG_PLL,0x03);
	status=Read_TWI_8bit_Reg(ADAU1979_REG_PLL);
	while(delay1--)
	{
		asm("nop;");
	}

	while(!((status & 0x80)>>7)  )
	{
		status=Read_TWI_8bit_Reg(ADAU1979_REG_PLL);
		asm("nop;");
	}

	return eResult;

}

//#define BYPASS_SS
int32_t nTempBuff[BLOCK_SIZE*(NUM_CHANNELS+NUM_CHANNELS2)];
void main(int32_t argc, char *argv[])
{
	/**
	 * Initialize managed drivers and/or services that have been added to
	 * the project.
	 * @return zero on success
	 */
	uint32_t Result=0, i, j;
	ADI_SS_MEM_BLOCK oConnectionMemBlk, *pConnectionMemBlk;
	ADI_SS_CONNECTION_CONFIG oConnConfig, *pConnConfig;
	ADI_SS_CONNECTION_RESULT eConnRet = ADI_SS_CONNECTION_FAILED;
	ADI_SS_CONNECTION_HANDLE hConnHandle;

	ADI_SS_MEM_BLOCK oCommMemBlk, *pCommMemBlk;
	ADI_SS_COMM_CONFIG oCommnConfig, *pCommnConfig;
	ADI_SS_COMM_RESULT eCommRet = ADI_SS_COMM_FAILED;
	ADI_SS_COMM_HANDLE hCommHandle;

	ADI_SS_RESULT eSSRes;
	SS_SMAP_SSN_INFO    *pSSnInfo;
	ADI_SS_COMM_PROPERTIES pCommProp;
	int32_t *pSportIn, *pSportOut, *pSportIn1, *pSportOut1;

	adi_initComponents();
	PCG_init();
   /* SPU initialization */
	if (Result==0u)
	{
		Result=SPU_init();
	}

	/* Switch Configuration */
	//Switch_Configurator();

	/* SRU Configuration */
	SRU_Init();

	/* TWI Initialization */
	if (Result==0u)
	{
		//Result=Init_TWI();
	}

	/* ADAU1962 Initialization */
	if (Result==0u)
	{
		//Result=ADAU_1962_init();
	}

	/* ADAU1979 Initialization */
	if (Result==0u)
	{
		//Result=ADAU_1979_init();
	}

	/*******************************************************************************/
	/* SigmaStudio for SHARC (ADSP-SC5xx/ADSP-215xx) library integration */

	/* Connection component Initialization */
	pConnConfig = &oConnConfig;
	pConnConfig->eConnectionType = ADI_SS_CONNECTION_SPI;
	pConnConfig->nDevId = 1;
    pConnConfig->eProcID = PROCESSOR_SH0;

	pConnectionMemBlk = &oConnectionMemBlk;
	pConnectionMemBlk->nSize = ADI_SS_CONNECTION_MEMSIZE;
	pConnectionMemBlk->pMem = adi_ss_connection_mem;
	eConnRet = adi_ss_connection_Init(pConnectionMemBlk, pConnConfig, &hConnHandle);
	if(eConnRet != ADI_SS_CONNECTION_SUCCESS)
	{
        printf("\nConnection component initialization failed");
        exit(-1);
	}

	/* Communication component initialization*/
	pCommnConfig = &oCommnConfig;
	pCommnConfig->bCRCBypass = false;
	pCommnConfig->bFullPacketCRC = true;
	pCommnConfig->pfCommCmd4CallBack = (ADI_SS_COMM_CMD4_CB) adi_ss_comm_callback_cmd4;
	pCommnConfig->pfCommSMAPCallBack = (ADI_SS_COMM_SMAP_CB) adi_SMAP_Application_Callback;
	pCommnConfig->hConnectionHandle = hConnHandle;
	pCommnConfig->pMemSMap[PROCESSOR_SH0] = &oSMAPSharc0;
	pCommnConfig->pBkChnlInfo[0] = &oBkChannelInfoSharc0;

	pCommMemBlk = &oCommMemBlk;
	pCommMemBlk->nSize = ADI_SS_COMM_MEMSIZE;
	pCommMemBlk->pMem = adi_ss_commn_mem;
	eCommRet = adi_ss_comm_Init(pCommMemBlk, pCommnConfig, &hCommHandle);
	if(eCommRet != ADI_SS_COMM_SUCCESS)
	{
        printf("\nCommunication component initialization failed");
        exit(-1);
	}

	/* Wait for SMAP to be received from host */
	/*while(!nSMAPReceived)
	{

	}*/
	memcpy(&oSMAPSharc0, adi_ss_smap_IC_1, adi_ss_smap_IC_1_size*4);
	/* Populating Memory addresses of different blocks from SMAP */
	oSSnMemMap.nMemBlocks = 11;
	pSSnInfo = &oSMAPSharc0.oSSnInfo[0];
	for(i=0; i<oSSnMemMap.nMemBlocks; i++)
	{
		oSSnMemMap.pMemBlocks[i] = &pSSnInfo->oSSnBuff[i];
	}

	/* Create an instance of SSn */
	adi_ss_create( &hSSnHandle, &oSSnMemMap);
	if(hSSnHandle == NULL)
	{
		printf("\n SSn instance creation failed");
		exit(-1);
	}

	/* Provide SSn handle to communication component using the adi_ss_comm_SetProperties() API */
	pCommProp.haSSnHandle[PROCESSOR_SH0][0] = hSSnHandle;
	pCommProp.nNumProcBlocks = 1;
	pCommProp.nProcId = PROCESSOR_SH0;
	eCommRet = adi_ss_comm_SetProperties(hCommHandle,ADI_COMM_PROP_SSN_HANDLE,&pCommProp);
    if(eCommRet != ADI_SS_COMM_SUCCESS)
	{
		printf("\nError in Communication component");
		exit(-1);
	}

	/* Initialize the SSn instance */
	pSSnConfig = &oSSnConfig;
	pSSnConfig->hSSComm = hCommHandle;
	pSSnConfig->nBlockSize = BLOCK_SIZE ;
	pSSnConfig->nInChannels = NUM_CHANNELS+NUM_CHANNELS2;
	pSSnConfig->nOutChannels = NUM_CHANNELS+NUM_CHANNELS2;
	pSSnConfig->bSkipProcessOnCRCError = 0;
	pSSnConfig->bSkipInitialDownload = 1U;
	pSSnConfig->nInitNoWait = 1;
	pSSnConfig->eProcID = PROCESSOR_SH0;
	pSSnConfig->bClearUnusedOutput = 1;

	/* copy code from schematic source file */
	memcpy(oSSnMemMap.pMemBlocks[1]->pMem, adi_ss_code_IC_1, adi_ss_code_IC_1_size*2);

	/* copy parameter from schematic source file */
	memcpy(oSSnMemMap.pMemBlocks[5]->pMem, adi_ss_param_IC_1, adi_ss_param_IC_1_size*4);


	eSSRes =  adi_ss_init(hSSnHandle, pSSnConfig);
	if(eSSRes != ADI_SS_SUCCESS)
	{
		printf("\nSSn instance initialization failed");
		exit(-1);
	}

	pSSnProperties = &oSSnProperties;

	/* Initialize SigmaStudio I/O pointers */
	for(i=0; i<NUM_CHANNELS+NUM_CHANNELS2; i++)
	{
		pSSInBuff[i] = &aSSInOutBuff[i*BLOCK_SIZE];
		pSSOutBuff[i] = pSSInBuff[i];
	}

	/* Populating hardcoded values for readback */
	for(i=0; i<2; i++)
	{
		oBkChannelInfoSharc0.nAvgMIPS[i]=10.0;
		oBkChannelInfoSharc0.nPeakMIPS[i]=20.0;
		oBkChannelInfoSharc0.nVersionInfo=0x47000000;
	}

	/*******************************************************************************/

	/* SPORT Initialization */
	if (Result==0u)
	{
		Result=Sport_Init();
	}

	/* Close TWI */
	if (Result==0u)
	{
		//Result=Stop_TWI();
	}

	while(1)
	{
#ifdef BYPASS_SS
		if(nDataAvail >= 1)
		{
			nDataAvail = 0;

			if(CallbackCount == 1)
			{
				pSportIn = &int_SP0ABuffer4[0];
				pSportOut = &int_SP0ABuffer1[0];
			}
			else if(CallbackCount == 2)
			{
				pSportIn = &int_SP0ABuffer5[0];
				pSportOut = &int_SP0ABuffer2[0];
				CallbackCount=0;
			}

		   for(i=0,j=0;i<BLOCK_SIZE*NUM_CHANNELS;i+=NUM_CHANNELS,j+=NUM_CHANNELS)
		   {
			   /*Copy ADC buffer to DAC buffer */
			   pSportOut[j]  = pSportIn[i];
			   pSportOut[j+4] = pSportIn[i];
			   pSportOut[j+1] = pSportIn[i+1];
			   pSportOut[j+5] = pSportIn[i+1];
			   pSportOut[j+2] = pSportIn[i+2];
			   pSportOut[j+6] = pSportIn[i+2];
			   pSportOut[j+3] = pSportIn[i+3];
			   pSportOut[j+7] = pSportIn[i+3];
		   }
		}
#else
		if(nDataAvail >= 1)
		{
			nDataAvail = 0;

			if(CallbackCount == 1)
			{
				pSportIn = &int_SP0ABuffer4[0];
				pSportOut = &int_SP0ABuffer1[0];
				pSportIn1 = &int_SP0ABuffer4[0];
				pSportOut1 = &int_SP0ABuffer6[0];
			}
			else if(CallbackCount == 2)
			{
				pSportIn = &int_SP0ABuffer5[0];
				pSportOut = &int_SP0ABuffer2[0];
				pSportIn1 = &int_SP0ABuffer5[0];
				pSportOut1 = &int_SP0ABuffer7[0];
				CallbackCount=0;
			}

			memcpy(nTempBuff,pSportIn,BLOCK_SIZE*NUM_CHANNELS*sizeof(int));
			memcpy(&nTempBuff[16*BLOCK_SIZE],pSportIn1,BLOCK_SIZE*NUM_CHANNELS2*sizeof(int));

			/* Fixed to float conversion and copy to SS input buffer */
			for(i=0; i<NUM_CHANNELS+NUM_CHANNELS2; i++)
			{
				//CopyFix2Float((volatile uint32_t*)&pSportIn[i], NUM_CHANNELS, pSSInBuff[i], 1, BLOCK_SIZE, 1u);
				CopyFix2Float((volatile uint32_t*)&nTempBuff[i], NUM_CHANNELS+NUM_CHANNELS2, pSSInBuff[i], 1, BLOCK_SIZE, 1u);
			}


			/* Call to the Schematic processing  */
			adi_ss_schematic_process(hSSnHandle,BLOCK_SIZE,(adi_ss_sample_t **)pSSInBuff,(adi_ss_sample_t **)pSSOutBuff,pSSnProperties);

			/* Float to fix conversion and copy back to SPORT buffer */
			for(i=0; i<NUM_CHANNELS+NUM_CHANNELS2; i++)
			{
				if(i<NUM_CHANNELS)
					CopyFloat2Fix(pSSOutBuff[i], 1, (volatile uint32_t * )&pSportOut[i], NUM_CHANNELS, BLOCK_SIZE, 0u);
				else
					CopyFloat2Fix(pSSOutBuff[i], 1, (volatile uint32_t * )&pSportOut1[i-NUM_CHANNELS], NUM_CHANNELS2, BLOCK_SIZE, 0u);
			}

			if(nDataAvail >= 1)
			{
				printf("\n Input buffer overflow detected");
				exit(-1);
			}
		}
#endif
	}
}


void adi_SMAP_Application_Callback(ADI_SS_PROC_ID eCoreID)
{
	if(eCoreID==PROCESSOR_SH0)
	{
		nSMAPReceived = 1;
	}
}



void adi_ss_comm_callback_cmd4(uint32_t *pCommPayloadBuff, int32_t  nPayloadCount, ADI_SS_SSN_HANDLE hSSn)
{
	;
}

hi VSankar

I have write a example code below, can you help me check if there is any issues in the buffer ,memory copy or other issues?  the code init 3 sports , 0B for receive(TDM16 BCLK:24.576M  FRAME SYNC: 48K  32BIT) , 4A for transmit (BCLK:24.576M  FRAME SYNC: 48K  32BIT) ,5A for another transmit of the data receive by sport 0B in tdm8 (BCLK:12.288M  FRAME SYNC: 48K  32BIT).

/*****************************************************************************
Copyright (c) 2019-2023 Analog Devices Inc. All rights reserved
This software is proprietary & confidential to Analog Devices, Inc.
and its licensors.
*****************************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <sys/platform.h>
#include <sys/adi_core.h>
#include "adi_initialize.h"
#include <services/int/adi_int.h>
#include <drivers/sport/adi_sport.h>
#include <services/spu/adi_spu.h>
#include <drivers/twi/adi_twi_2156x.h>
#include "ADAU_1962Common.h"
#include "ADAU_1979Common.h"
#include <cdef21569.h>
#include "math.h"
#include <string.h>
#include <sru21569.h>
#include "LibIntegrationExample_Core1.h"
#include "adi_ss_smap.h"
#include "adi_ss_ssn_export_export_DiffDXESchematic_IC_1.h"
#include "adi_ss_utility.h"
#include <services/pcg/adi_pcg.h>

#ifdef DO_CYCLE_COUNTS
#include "cycles.h"
#endif

/******* SigmaStudio Integration ***************/

#define ADI_SS_APP_DELAY_100_MSEC (100 * 10000)
/*Defining Backchannel info structure. Will be populated by the framework */
typedef struct ADI_SS_BACKCH_INFO
{
    float32_t    nPeakMIPS[ADI_SS_FW_MAX_PROC_BLOCKS]; /*!< Peak MIPS for all process blocks */
    float32_t    nAvgMIPS[ADI_SS_FW_MAX_PROC_BLOCKS];  /*!< Average MIPS for all process blocks */
    uint32_t     nVersionInfo;                  	   /*!< Target library API version */
    uint32_t     nSSnDownloadStatus;            	   /*!< Current download status of SSns within all process blocks*/
}ADI_SS_BACKCH_INFO;

#include "adi_ss_connection.h"
#include "adi_ss_communication.h"
#include "adi_ss_ssn.h"

/* Memory for SigmaStudio for Griffin libraries */
/* Connection and Communication Instance Mem */
#pragma align(4)
#pragma section("ss_app_data0_fast")
uint8_t adi_ss_commn_mem[ADI_SS_COMM_MEMSIZE];
#pragma align(4)
#pragma section("ss_app_data0_fast")
uint8_t adi_ss_connection_mem[ADI_SS_CONNECTION_MEMSIZE];

bool bSportCallback;
volatile uint32_t nSMAPReceived=0;

/* SMAP */
ADI_SS_MEM_SMAP oSMAPSharc0;
ADI_SS_MEM_MAP oSSnMemMap;

/* SSn Config structure */
ADI_SS_CONFIG  *pSSnConfig,oSSnConfig;

/* SSnProperties structure */
ADI_SS_SSNPROPERTIES *pSSnProperties,oSSnProperties;

/* Defining SSn Handle */
ADI_SS_SSN_HANDLE hSSnHandle;

/* Backchannel info */
ADI_SS_BACKCH_INFO 	oBkChannelInfoSharc0;

/* I/O buffer and pointers for SSn instance */
float32_t aSSInOutBuff[BLOCK_SIZE*(NUM_CHANNELS+NUM_CHANNELS2)];
float32_t *pSSInBuff[NUM_CHANNELS+NUM_CHANNELS2];
float32_t *pSSOutBuff[NUM_CHANNELS+NUM_CHANNELS2];

void adi_ss_comm_callback_cmd4(uint32_t  *pCommPayloadBuff,
                               int32_t   nPayloadCount,
                               ADI_SS_SSN_HANDLE hSSn);

void adi_SMAP_Application_Callback(ADI_SS_PROC_ID eCoreID);

/* Convert the audio samples generated by ADC into float format */
void    CopyFix2Float( volatile        uint32_t  *pInBuffer,
                                        uint32_t nInStride,
                       volatile        float    *pOutBuffer,
                                        uint32_t nOutStride,
                                        uint32_t nBlockSize,
                                        uint32_t nShiftFlag);

/* Convert the audio samples from float to fixed point (which can be consumed by DAC) */
uint32_t CopyFloat2Fix(volatile   float *pInBuffer,
                                        uint32_t nInStride,
                               volatile uint32_t *pOutBuffer,
                                        uint32_t nOutStride,
                                        uint32_t nBlockSize,
                                        uint32_t nShiftFlag);

/******* SigmaStudio Integration END  ***************/


/* SPORT buffers */
int32_t int_SP0ABuffer1[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer2[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer4[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer5[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer6[BLOCK_SIZE*NUM_CHANNELS2];
int32_t int_SP0ABuffer7[BLOCK_SIZE*NUM_CHANNELS2];

struct Config_Table
{
	short Reg_Add;
	char  Value;
};

char Config_read_DAC[28];
char Config_read_ADC[16];

/* Dev buffer for configuring ADC-DAC through TWI*/
static uint8_t devBuffer[BUFFER_SIZE];

extern void ConfigSoftSwitches_ADC_DAC(void);

extern void ConfigSoftSwitches_ADAU_Reset(void);

#if 0
struct Config_Table Config_array_DAC[28] = {
		   	    {     ADAU1962_PDN_CTRL_1,		0x00},
		   	    {     ADAU1962_PDN_CTRL_2,	    0xff},
		   	    {     ADAU1962_PDN_CTRL_3,	    0x0f},
		   	    {     ADAU1962_DAC_CTRL0,		0x01},
		   	    {     ADAU1962_DAC_CTRL1,		0x41},
		   	    {     ADAU1962_DAC_CTRL2,		0x00},
		   	    {     ADAU1962_DAC_MUTE1,	    0x0},
		   	    {     ADAU1962_DAC_MUTE2,	    0x00},
		   	    {     ADAU1962_MSTR_VOL,		0x00},
			    {     ADAU1962_DAC1_VOL,	    0x00},
			    {     ADAU1962_DAC2_VOL,		0x00},
				{     ADAU1962_DAC3_VOL,		0x00},
				{     ADAU1962_DAC4_VOL,		0x00},
				{     ADAU1962_DAC5_VOL,		0x00},
				{     ADAU1962_DAC6_VOL,		0x00},
				{     ADAU1962_DAC7_VOL,		0x00},
				{     ADAU1962_DAC8_VOL,	    0x00},
				{     ADAU1962_DAC9_VOL,		0x00},
				{     ADAU1962_DAC10_VOL,		0x00},
				{     ADAU1962_DAC11_VOL,		0x00},
				{     ADAU1962_DAC12_VOL,		0x00},
				{     ADAU1962_PAD_STRGTH,		0x00},
				{     ADAU1962_DAC_PWR1,		0xaa},
				{     ADAU1962_DAC_PWR2,		0xaa},
				{     ADAU1962_DAC_PWR3,		0xaa},
				{     ADAU1962_PDN_CTRL_2,	    0x00},
				{     ADAU1962_PDN_CTRL_3,	    0x00},
				{     ADAU1962_DAC_CTRL0,		0x18}

};
#else
struct Config_Table Config_array_DAC[28] = {
		   	    {     ADAU1962_PDN_CTRL_1,		0xa4 },
		   	    {     ADAU1962_PDN_CTRL_2,	    0xff },  //Power down DAC
		   	    {     ADAU1962_PDN_CTRL_3,	    0x0f }, //Power down DAC
		   	    {     ADAU1962_DAC_CTRL0,		0x19 },
		   	    {     ADAU1962_DAC_CTRL1,		0x63 }, // pulse mode LRCLK, MSB first //orginal value =42
		   	    {     ADAU1962_DAC_CTRL2,		0x04 },  // TDM Configuration
		   	    {     ADAU1962_DAC_MUTE1,	    0x00 },
		   	    {     ADAU1962_DAC_MUTE2,	    0x00 },
		   	    {     ADAU1962_MSTR_VOL,		0x00 },
			    {     ADAU1962_DAC1_VOL,	    0x00 } ,
			    {     ADAU1962_DAC2_VOL,		0x00 },
				{     ADAU1962_DAC3_VOL,		0x00 },
				{     ADAU1962_DAC4_VOL,		0x00 },
				{     ADAU1962_DAC5_VOL,		0x00 },
				{     ADAU1962_DAC6_VOL,		0x00 },
				{     ADAU1962_DAC7_VOL,		0x00 },
				{     ADAU1962_DAC8_VOL,	    0x00 },
				{     ADAU1962_DAC9_VOL,		0x00 },
				{     ADAU1962_DAC10_VOL,		0x00 },
				{     ADAU1962_DAC11_VOL,		0x00 },
				{     ADAU1962_DAC12_VOL,		0x00 },
				{     ADAU1962_PAD_STRGTH,		0x00 },
				{     ADAU1962_DAC_PWR1,		0xaa },
				{     ADAU1962_DAC_PWR2,		0xaa },
				{     ADAU1962_DAC_PWR3,		0xaa },
				{     ADAU1962_PDN_CTRL_2,	    0x00 },
				{     ADAU1962_PDN_CTRL_3,	    0x00 },
		   	    {     ADAU1962_DAC_CTRL0,		0x18 },
};
#endif

#if 0
struct Config_Table Config_array_ADC[16] = {

		 {ADAU1979_REG_BOOST			,	0x00},
		 {ADAU1979_REG_MICBIAS			,	0x00},
		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0x30},
		 /*{ADAU1979_REG_SAI_CTRL0		,	0x1B}, */
		 {ADAU1979_REG_SAI_CTRL0		,	0x1A},/*I2S format*/
		 {ADAU1979_REG_SAI_CTRL1		,	0x08},
		 {ADAU1979_REG_CMAP12			,	0x10},
		 {ADAU1979_REG_CMAP34			,	0x32},
		 {ADAU1979_REG_SAI_OVERTEMP		,	0xf0},
		 {ADAU1979_REG_POST_ADC_GAIN1 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN2 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN3 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN4 	,	0xA0},
		 {ADAU1979_REG_ADC_CLIP			,	0x00},
		 {ADAU1979_REG_DC_HPF_CAL		,	0x00},
		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0x3f},
		 {ADAU1979_REG_MISC_CONTROL		,	0x02}
};
#else
struct Config_Table Config_array_ADC[16] = {

		 {ADAU1979_REG_BOOST			,	0x00},
		 {ADAU1979_REG_MICBIAS			,	0x00},
 		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0xb0},//power down ADC LDO enabel
		 {ADAU1979_REG_SAI_CTRL0		,	0x5a},//TDM 48kHz
		 {ADAU1979_REG_SAI_CTRL1		,	0x08},//LRCLK pulse mode //original value =08
		 {ADAU1979_REG_CMAP12			,	0x10},
		 {ADAU1979_REG_CMAP34			,	0x32},
		 {ADAU1979_REG_SAI_OVERTEMP		,	0xf0},
		 {ADAU1979_REG_POST_ADC_GAIN1 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN1 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN3 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN4 	,	0xA0},
		 {ADAU1979_REG_ADC_CLIP			,	0x00},
		 {ADAU1979_REG_DC_HPF_CAL		,	0x00},// filter off
		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0xbf},//power on  ADC LDO enable
		 {ADAU1979_REG_MISC_CONTROL		,	0x02},//mute all channels
};
#endif

/* Destination PDMA lists */
ADI_PDMA_DESC_LIST iDESC_LIST_1_SP4A;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP4A ;

/* Source PDMA lists */
ADI_PDMA_DESC_LIST iSRC_LIST_1_SP0B ;
ADI_PDMA_DESC_LIST iSRC_LIST_2_SP0B ;

/* Destination PDMA lists */
ADI_PDMA_DESC_LIST iDESC_LIST_1_SP5A;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP5A ;

/* Prepares descriptors for SPORT DMA */
static void PrepareDescriptors (void);

/* Count to track the number of callBacks for SPORT transfer */
volatile uint8_t CallbackCount = 0;
volatile uint32_t TestCallbackCount = 0;
volatile uint32_t nDataAvail=0;


/* Memory required for SPORT */
static uint8_t SPORTMemory4A[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory0B[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory5A[ADI_SPORT_MEMORY_SIZE];

/* SPORT Handle */
static ADI_SPORT_HANDLE hSPORTDev4ATx;//TX
static ADI_SPORT_HANDLE hSPORTDev0BRx;//RX
static ADI_SPORT_HANDLE hSPORTDev5ATx;//TX

/* Memory required for TWI */
uint8_t TwideviceMemory[ADI_TWI_MEMORY_SIZE];

/* TWI driver handle */
static ADI_TWI_HANDLE hTwiDevice;

/* SPU handle */
static ADI_SPU_HANDLE      ghSpu;

/* Memory required for the SPU operation */
uint8_t             SpuMemory[ADI_SPU_MEMORY_SIZE];

int32_t delay;

static int32_t ADAU_1962_Pllinit(void);
static int32_t ADAU_1979_Pllinit(void);
void Switch_Configurator(void);
static int32_t ADAU_1962_init(void);
static int32_t ADAU_1979_init(void);
void SRU_Init(void);
static int32_t Sport_Init(void);
static int32_t Sport_Stop(void);
static int32_t SPU_init(void);
static void PrepareDescriptors (void);
static int32_t Init_TWI(void);
static int32_t Stop_TWI(void);
static void PCG_init(void);

static void PCG_init(void)
{

	ADI_PCG_CLK_INFO gClkInfoC;
			gClkInfoC.eClkInput = ADI_PCG_CLK_CLKIN0;               /* Clock Source */
			gClkInfoC.nDiv = 1;                 /* Clock Divisor */
			gClkInfoC.bExternalTrigger = false;                    /* External Trigger */


	ADI_PCG_FS_INFO gFsInfoC;
			gFsInfoC.eClkInput = ADI_PCG_FS_CLKIN0;                               /* Clock Source */
			gFsInfoC.nDiv = (gClkInfoC.nDiv)*(ADI_SPORT0A_CTL_SLEN + 1)*(NUM_CHANNELS);     /* Frame Sync Divisor */
			gFsInfoC.nPulseWidth = 1;                            /* Pulse Width */
			gFsInfoC.nPhase = 2;                                /* Phase */
			gFsInfoC.bExternalTrigger = false;                                   /* External Trigger */
			gFsInfoC.eFsBypassMode = ADI_PCG_FSBYPASS_MODE_NORMAL;               /* Bypass Mode */

			adi_pcg_Init(ADI_PCG_DEV_C,&gClkInfoC,&gFsInfoC);

	ADI_PCG_CLK_INFO gClkInfoD;
				gClkInfoD.eClkInput = ADI_PCG_CLK_CLKIN0;               /* Clock Source */
				gClkInfoD.nDiv = 2;                 /* Clock Divisor */
				gClkInfoD.bExternalTrigger = false;                    /* External Trigger */


	ADI_PCG_FS_INFO gFsInfoD;
			gFsInfoD.eClkInput = ADI_PCG_FS_CLKIN0;                               /* Clock Source */
			gFsInfoD.nDiv = (gClkInfoD.nDiv)*(ADI_SPORT5A_CTL_SLEN + 1)*(NUM_CHANNELS2);     /* Frame Sync Divisor */
			gFsInfoD.nPulseWidth = 1;                            /* Pulse Width */
			gFsInfoD.nPhase = 2;                                /* Phase */
			gFsInfoD.bExternalTrigger = false;                                   /* External Trigger */
			gFsInfoD.eFsBypassMode = ADI_PCG_FSBYPASS_MODE_NORMAL;               /* Bypass Mode */

			adi_pcg_Init(ADI_PCG_DEV_D,&gClkInfoD,&gFsInfoD);



}
static void SPORTCallback(void        *pAppHandle,
						  uint32_t     nEvent,
						  void        *pArg
						 )
{
	int32_t i;
	int32_t j;

	ADI_SPORT_RESULT eResult;
    /* CASEOF (event type) */
    switch (nEvent)
    {
        /* CASE (buffer processed) */
        case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
        		TestCallbackCount += 1;
        		CallbackCount += 1;
        		nDataAvail += 1;
        		break;
        default:
        	 break;
    }
    /* return */
}

/*
 * Prepares descriptors for Memory DMA copy.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */

static void PrepareDescriptors (void)
{

	iDESC_LIST_1_SP4A.pStartAddr	= (int32_t *)int_SP0ABuffer1;
	iDESC_LIST_1_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_1_SP4A.XCount		= BLOCK_SIZE*NUM_CHANNELS;
	iDESC_LIST_1_SP4A.XModify		= 4;
	iDESC_LIST_1_SP4A.YCount		= 0;
	iDESC_LIST_1_SP4A.YModify		= 0;
	iDESC_LIST_1_SP4A.pNxtDscp		= &iDESC_LIST_2_SP4A;

	iDESC_LIST_2_SP4A.pStartAddr	= (int32_t *)int_SP0ABuffer2;
	iDESC_LIST_2_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_2_SP4A.XCount		= BLOCK_SIZE*NUM_CHANNELS;
	iDESC_LIST_2_SP4A.XModify		= 4;
	iDESC_LIST_2_SP4A.YCount		= 0;
	iDESC_LIST_2_SP4A.YModify		= 0;
	iDESC_LIST_2_SP4A.pNxtDscp		= &iDESC_LIST_1_SP4A;

	iSRC_LIST_1_SP0B.pStartAddr		=(int32_t *)int_SP0ABuffer4;
	iSRC_LIST_1_SP0B.Config			= ENUM_DMA_CFG_XCNT_INT ;
	iSRC_LIST_1_SP0B.XCount			= BLOCK_SIZE*NUM_CHANNELS;
	iSRC_LIST_1_SP0B.XModify		= 4;
	iSRC_LIST_1_SP0B.YCount			= 0;
	iSRC_LIST_1_SP0B.YModify		= 0;
	iSRC_LIST_1_SP0B.pNxtDscp		= &iSRC_LIST_2_SP0B;

	iSRC_LIST_2_SP0B.pStartAddr		=(int32_t *)int_SP0ABuffer5;
	iSRC_LIST_2_SP0B.Config			= ENUM_DMA_CFG_XCNT_INT;
	iSRC_LIST_2_SP0B.XCount			= BLOCK_SIZE*NUM_CHANNELS;
	iSRC_LIST_2_SP0B.XModify		= 4;
	iSRC_LIST_2_SP0B.YCount			= 0;
	iSRC_LIST_2_SP0B.YModify		= 0;
	iSRC_LIST_2_SP0B.pNxtDscp		= &iSRC_LIST_1_SP0B;

	iDESC_LIST_1_SP5A.pStartAddr	= (int32_t *)int_SP0ABuffer6;
	iDESC_LIST_1_SP5A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_1_SP5A.XCount		= BLOCK_SIZE*NUM_CHANNELS2;
	iDESC_LIST_1_SP5A.XModify		= 4;
	iDESC_LIST_1_SP5A.YCount		= 0;
	iDESC_LIST_1_SP5A.YModify		= 0;
	iDESC_LIST_1_SP5A.pNxtDscp		= &iDESC_LIST_2_SP5A;

	iDESC_LIST_2_SP5A.pStartAddr	= (int32_t *)int_SP0ABuffer7;
	iDESC_LIST_2_SP5A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_2_SP5A.XCount		= BLOCK_SIZE*NUM_CHANNELS2;
	iDESC_LIST_2_SP5A.XModify		= 4;
	iDESC_LIST_2_SP5A.YCount		= 0;
	iDESC_LIST_2_SP5A.YModify		= 0;
	iDESC_LIST_2_SP5A.pNxtDscp		= &iDESC_LIST_1_SP5A;


}

static int32_t Sport_Init()
{
    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

	/* Open the SPORT Device 4A */
	eResult = adi_sport_Open(SPORT_DEVICE_4A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_MC_MODE, SPORTMemory4A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/* Open the SPORT Device 0B*/
	eResult = adi_sport_Open(SPORT_DEVICE_0B,ADI_HALF_SPORT_B,ADI_SPORT_DIR_RX, ADI_SPORT_MC_MODE, SPORTMemory0B,ADI_SPORT_MEMORY_SIZE,&hSPORTDev0BRx);
	CHECK_RESULT(eResult);
	/* Open the SPORT Device 4A */
	eResult = adi_sport_Open(SPORT_DEVICE_5A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_MC_MODE, SPORTMemory5A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev5ATx);
	CHECK_RESULT(eResult);


	/* Configure the data,clock,frame sync and MCTL of SPORT Device 4A*/
	eResult = adi_sport_ConfigData(hSPORTDev4ATx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigClock(hSPORTDev4ATx,32,false,/*false*/ true,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigFrameSync(hSPORTDev4ATx,31,false,false,true,/*true*/ false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigMC(hSPORTDev4ATx,0u,15u,0u,true);
	CHECK_RESULT(eResult);
	eResult = adi_sport_SelectChannel(hSPORTDev4ATx,0u,15u);
	CHECK_RESULT(eResult);

	/* Configure the data,clock,frame sync and MCTL of SPORT Device 0B*/
	eResult = adi_sport_ConfigData(hSPORTDev0BRx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigClock(hSPORTDev0BRx,32,false,/*false*/ false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigFrameSync(hSPORTDev0BRx,31,false,false,true,/*true*/ true,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigMC(hSPORTDev0BRx,0u,15u,0u,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_SelectChannel(hSPORTDev0BRx,0u,15u);
	CHECK_RESULT(eResult);

	/* Configure the data,clock,frame sync and MCTL of SPORT Device 5A*/
	eResult = adi_sport_ConfigData(hSPORTDev5ATx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigClock(hSPORTDev5ATx,32,false,/*false*/ true,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigFrameSync(hSPORTDev5ATx,31,false,false,true,/*true*/ false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigMC(hSPORTDev5ATx,0u,7u,0u,true);
	CHECK_RESULT(eResult);
	eResult = adi_sport_SelectChannel(hSPORTDev5ATx,0u,7u);
	CHECK_RESULT(eResult);

	/* Register SPORT Callback function */
	eResult = adi_sport_RegisterCallback(hSPORTDev0BRx,SPORTCallback,NULL);
	CHECK_RESULT(eResult);

	/* Prepare descriptors */
	PrepareDescriptors();

	/* Submit the first buffer for Rx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev0BRx,&iSRC_LIST_1_SP0B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);
	/* Submit the first buffer for Tx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev4ATx,&iDESC_LIST_1_SP4A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);

	/* Submit the first buffer for Tx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev5ATx,&iDESC_LIST_1_SP5A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);

	/*Enable the Sport Device 0B */
	eResult = adi_sport_Enable(hSPORTDev0BRx,true);
	CHECK_RESULT(eResult);
	/*Enable the Sport Device 4A */
	eResult = adi_sport_Enable(hSPORTDev4ATx,true);
	CHECK_RESULT(eResult);
	/*Enable the Sport Device 5A */
	eResult = adi_sport_Enable(hSPORTDev5ATx,true);
	CHECK_RESULT(eResult);

	return eResult;

}

static int32_t Sport_Stop(void)
{
    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

    /*Stop the DMA transfer of  Sport Device 0B */
	eResult = adi_sport_StopDMATransfer(hSPORTDev0BRx);
	CHECK_RESULT(eResult);
	/*Stop the DMA transfer of  Sport Device 4A */
	eResult = adi_sport_StopDMATransfer(hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/*Stop the DMA transfer of  Sport Device 5A */
	eResult = adi_sport_StopDMATransfer(hSPORTDev5ATx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 0B */
	eResult = adi_sport_Close(hSPORTDev0BRx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 4A */
	eResult = adi_sport_Close(hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 5A */
	eResult = adi_sport_Close(hSPORTDev5ATx);
	CHECK_RESULT(eResult);

	return eResult;
}

/*
 * Prepares Switch configuration.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */
void Switch_Configurator()
{
	int32_t delay11=0xffff;


	/* Software Switch Configuration for Re-Setting ADC-DAC  */
	ConfigSoftSwitches_ADAU_Reset();

	while(delay11--)
	{
		asm("nop;");
	}

	/* Software Switch Configuration for Enabling ADC-DAC */
	ConfigSoftSwitches_ADC_DAC();

	/* wait for Codec to up */
	delay11=0xffff;
	while(delay11--)
	{
		asm("nop;");
	}
}



/*
 * Prepares SRU configuration.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */
void SRU_Init()
{
	*pREG_PADS0_DAI0_IE=0xfffff;
	*pREG_PADS0_DAI1_IE=0xfffff;

	// SPORT 0B configuration
	SRU(LOW,DAI0_PBEN05_I);
	SRU(DAI0_PB05_O,SPT0_BD0_I);
	SRU(LOW,DAI0_PBEN07_I);
	SRU(DAI0_PB07_O,SPT0_BCLK_I);
	SRU(LOW,DAI0_PBEN08_I);
	SRU(DAI0_PB08_O,SPT0_BFS_I);

	// SPORT 4A configuration
	SRU2(HIGH,DAI1_PBEN01_I);
	SRU2(SPT4_AD0_O,DAI1_PB01_I);

	SRU2(HIGH,DAI1_PBEN03_I);
	SRU2(PCG0_CLKC_O,DAI1_PB03_I);
	SRU2(PCG0_FSC_O,DAI1_PB04_I);
	SRU2(HIGH,DAI1_PBEN04_I);

	SRU2(PCG0_CLKC_O,SPT4_ACLK_I);
	SRU2(PCG0_FSC_O,SPT4_AFS_I);

	// SPORT 5A configuration
	SRU2(HIGH,DAI1_PBEN10_I);
	SRU2(SPT5_AD0_O,DAI1_PB10_I);

	SRU2(HIGH,DAI1_PBEN20_I);
	SRU2(PCG0_CLKD_O,DAI1_PB20_I);
	SRU2(HIGH,DAI1_PBEN11_I);
	SRU2(PCG0_CLKD_O,DAI1_PB11_I);
	SRU2(PCG0_FSD_O,DAI1_PB12_I);
	SRU2(HIGH,DAI1_PBEN12_I);

	SRU2(PCG0_CLKD_O,SPT5_ACLK_I);
	SRU2(PCG0_FSD_O,SPT5_AFS_I);

	/*SRU2(HIGH,DAI1_PBEN03_I);
	SRU2(DAI1_CRS_PB03_O,DAI1_PB03_I);
	SRU2(DAI1_CRS_PB04_O,DAI1_PB04_I);
	SRU2(HIGH,DAI1_PBEN04_I);

	SRU2(DAI1_CRS_PB03_O,SPT4_ACLK_I);
	SRU2(DAI1_CRS_PB04_O,SPT4_AFS_I);*/

}

/*
 * Prepares SPU configuration.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */
int32_t SPU_init(void)
{
    if(adi_spu_Init(0, SpuMemory, NULL, NULL, &ghSpu) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to initialize SPU service\n");
		return FAILED;
    }

    /* Make SPORT 0A to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_4A_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT4A\n");
		return FAILED;
    }
    /* Make SPORT 0A to generate secure transactions */
       if(adi_spu_EnableMasterSecure(ghSpu, SPORT_5A_SPU, true) != ADI_SPU_SUCCESS)
       {
       	REPORT_ERROR("Failed to enable Master secure for SPORT5A\n");
   		return FAILED;
       }
    /* Make SPORT 0B to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_0B_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT0B\n");
		return FAILED;
    }

    return SUCCESS;
}

void Write_TWI_8bit_Reg(unsigned char Reg_ID, unsigned char Tx_Data)
{
	devBuffer[0] = Reg_ID;
	devBuffer[1] = Tx_Data;
	adi_twi_Write(hTwiDevice, devBuffer, 2u, false);
}

uint8_t Read_TWI_8bit_Reg(unsigned char Reg_ID)
{
	ADI_TWI_RESULT eResult;
	uint8_t Rx_Data;

	/* write register address */
	devBuffer[0] = Reg_ID;
	eResult = adi_twi_Write(hTwiDevice, devBuffer, 1u, true);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI write failed 0x%08X\n", eResult);
	}

	/* read register value */
	eResult = adi_twi_Read(hTwiDevice, &Rx_Data, 1u, false);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Read failed 0x%08X\n", eResult);
	}

	return Rx_Data;
}

static int32_t Init_TWI(void)
{
	ADI_TWI_RESULT eResult;

	eResult = adi_twi_Open(TWIDEVNUM, ADI_TWI_MASTER, &TwideviceMemory[0],
			   	ADI_TWI_MEMORY_SIZE, &hTwiDevice);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Open failed 0x%08X\n", eResult);
	}

	eResult = adi_twi_SetPrescale(hTwiDevice, PRESCALEVALUE);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Prescale failed 0x%08X\n", eResult);
	}

	eResult = adi_twi_SetBitRate(hTwiDevice, BITRATE);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Bitrate failed 0x%08X\n", eResult);
	}


	eResult = adi_twi_SetDutyCycle(hTwiDevice, DUTYCYCLE);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Duty cycle failed 0x%08X\n", eResult);
	}

	eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
	}

	return eResult;
}

static int32_t Stop_TWI(void)
{
	ADI_TWI_RESULT eResult;

	eResult = adi_twi_Close(hTwiDevice);
	CHECK_RESULT(eResult);

	return eResult;
}

/*****************************************************************************************************************************/

static int32_t ADAU_1962_init(void)
{
	int32_t i;
	ADAU_1962_Pllinit();
	for(i=0;i<28;i++)
	{
		/* write value */
		Write_TWI_8bit_Reg(Config_array_DAC[i].Reg_Add,Config_array_DAC[i].Value);
		Config_read_DAC[i]=Read_TWI_8bit_Reg(Config_array_DAC[i].Reg_Add);
		if(Config_array_DAC[i].Value!= Config_read_DAC[i])
		{
			DEBUG_INFORMATION("\n Configuring ADAU_1962 failed");
			return FAILED;
		}
	}

	return SUCCESS;
}

static int32_t ADAU_1962_Pllinit(void)
{
	int32_t status,delay1=0xffff;

	ADI_TWI_RESULT eResult;

   	eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR_1962);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
	}

	Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x01);
	while(delay1--)
	{
		asm("nop;");
	}

	Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x05);

	delay1=0xffff;
	while(delay1--)
	{
		asm("nop;");
	}

	Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1,0x22);
	delay1=0xffff;
	while(delay1--)
	{
		asm("nop;");
	}
	status=Read_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1);
	while(!((status & 0x4)>>2)  )
	{
		status=Read_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1);
	}

	return eResult;
}




static int32_t ADAU_1979_init(void)
{
	int32_t i;

	ADAU_1979_Pllinit();

	for(i=0; i<16; i++)
	{
		Write_TWI_8bit_Reg(Config_array_ADC[i].Reg_Add,Config_array_ADC[i].Value);
		Config_read_ADC[i]=Read_TWI_8bit_Reg(Config_array_ADC[i].Reg_Add);
		if(Config_array_ADC[i].Value!= Config_read_ADC[i])
		{
			DEBUG_INFORMATION("\n Configuring ADAU_1979 failed");
			return FAILED;
		}
	}

	return SUCCESS;
}

static int32_t ADAU_1979_Pllinit(void)
{

	int32_t status,delay1=0xffff;

	ADI_TWI_RESULT eResult;

   	eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR_1979);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
	}

   	Write_TWI_8bit_Reg(ADAU1979_REG_POWER,0x01);
	Write_TWI_8bit_Reg(ADAU1979_REG_PLL,0x03);
	status=Read_TWI_8bit_Reg(ADAU1979_REG_PLL);
	while(delay1--)
	{
		asm("nop;");
	}

	while(!((status & 0x80)>>7)  )
	{
		status=Read_TWI_8bit_Reg(ADAU1979_REG_PLL);
		asm("nop;");
	}

	return eResult;

}

//#define BYPASS_SS
int32_t nTempBuff[BLOCK_SIZE*(NUM_CHANNELS+NUM_CHANNELS2)];
void main(int32_t argc, char *argv[])
{
	/**
	 * Initialize managed drivers and/or services that have been added to
	 * the project.
	 * @return zero on success
	 */
	uint32_t Result=0, i, j;
	ADI_SS_MEM_BLOCK oConnectionMemBlk, *pConnectionMemBlk;
	ADI_SS_CONNECTION_CONFIG oConnConfig, *pConnConfig;
	ADI_SS_CONNECTION_RESULT eConnRet = ADI_SS_CONNECTION_FAILED;
	ADI_SS_CONNECTION_HANDLE hConnHandle;

	ADI_SS_MEM_BLOCK oCommMemBlk, *pCommMemBlk;
	ADI_SS_COMM_CONFIG oCommnConfig, *pCommnConfig;
	ADI_SS_COMM_RESULT eCommRet = ADI_SS_COMM_FAILED;
	ADI_SS_COMM_HANDLE hCommHandle;

	ADI_SS_RESULT eSSRes;
	SS_SMAP_SSN_INFO    *pSSnInfo;
	ADI_SS_COMM_PROPERTIES pCommProp;
	int32_t *pSportIn, *pSportOut, *pSportIn1, *pSportOut1;

	adi_initComponents();
	PCG_init();
   /* SPU initialization */
	if (Result==0u)
	{
		Result=SPU_init();
	}

	/* Switch Configuration */
	//Switch_Configurator();

	/* SRU Configuration */
	SRU_Init();

	/* TWI Initialization */
	if (Result==0u)
	{
		//Result=Init_TWI();
	}

	/* ADAU1962 Initialization */
	if (Result==0u)
	{
		//Result=ADAU_1962_init();
	}

	/* ADAU1979 Initialization */
	if (Result==0u)
	{
		//Result=ADAU_1979_init();
	}

	/*******************************************************************************/
	/* SigmaStudio for SHARC (ADSP-SC5xx/ADSP-215xx) library integration */

	/* Connection component Initialization */
	pConnConfig = &oConnConfig;
	pConnConfig->eConnectionType = ADI_SS_CONNECTION_SPI;
	pConnConfig->nDevId = 1;
    pConnConfig->eProcID = PROCESSOR_SH0;

	pConnectionMemBlk = &oConnectionMemBlk;
	pConnectionMemBlk->nSize = ADI_SS_CONNECTION_MEMSIZE;
	pConnectionMemBlk->pMem = adi_ss_connection_mem;
	eConnRet = adi_ss_connection_Init(pConnectionMemBlk, pConnConfig, &hConnHandle);
	if(eConnRet != ADI_SS_CONNECTION_SUCCESS)
	{
        printf("\nConnection component initialization failed");
        exit(-1);
	}

	/* Communication component initialization*/
	pCommnConfig = &oCommnConfig;
	pCommnConfig->bCRCBypass = false;
	pCommnConfig->bFullPacketCRC = true;
	pCommnConfig->pfCommCmd4CallBack = (ADI_SS_COMM_CMD4_CB) adi_ss_comm_callback_cmd4;
	pCommnConfig->pfCommSMAPCallBack = (ADI_SS_COMM_SMAP_CB) adi_SMAP_Application_Callback;
	pCommnConfig->hConnectionHandle = hConnHandle;
	pCommnConfig->pMemSMap[PROCESSOR_SH0] = &oSMAPSharc0;
	pCommnConfig->pBkChnlInfo[0] = &oBkChannelInfoSharc0;

	pCommMemBlk = &oCommMemBlk;
	pCommMemBlk->nSize = ADI_SS_COMM_MEMSIZE;
	pCommMemBlk->pMem = adi_ss_commn_mem;
	eCommRet = adi_ss_comm_Init(pCommMemBlk, pCommnConfig, &hCommHandle);
	if(eCommRet != ADI_SS_COMM_SUCCESS)
	{
        printf("\nCommunication component initialization failed");
        exit(-1);
	}

	/* Wait for SMAP to be received from host */
	/*while(!nSMAPReceived)
	{

	}*/
	memcpy(&oSMAPSharc0, adi_ss_smap_IC_1, adi_ss_smap_IC_1_size*4);
	/* Populating Memory addresses of different blocks from SMAP */
	oSSnMemMap.nMemBlocks = 11;
	pSSnInfo = &oSMAPSharc0.oSSnInfo[0];
	for(i=0; i<oSSnMemMap.nMemBlocks; i++)
	{
		oSSnMemMap.pMemBlocks[i] = &pSSnInfo->oSSnBuff[i];
	}

	/* Create an instance of SSn */
	adi_ss_create( &hSSnHandle, &oSSnMemMap);
	if(hSSnHandle == NULL)
	{
		printf("\n SSn instance creation failed");
		exit(-1);
	}

	/* Provide SSn handle to communication component using the adi_ss_comm_SetProperties() API */
	pCommProp.haSSnHandle[PROCESSOR_SH0][0] = hSSnHandle;
	pCommProp.nNumProcBlocks = 1;
	pCommProp.nProcId = PROCESSOR_SH0;
	eCommRet = adi_ss_comm_SetProperties(hCommHandle,ADI_COMM_PROP_SSN_HANDLE,&pCommProp);
    if(eCommRet != ADI_SS_COMM_SUCCESS)
	{
		printf("\nError in Communication component");
		exit(-1);
	}

	/* Initialize the SSn instance */
	pSSnConfig = &oSSnConfig;
	pSSnConfig->hSSComm = hCommHandle;
	pSSnConfig->nBlockSize = BLOCK_SIZE ;
	pSSnConfig->nInChannels = NUM_CHANNELS+NUM_CHANNELS2;
	pSSnConfig->nOutChannels = NUM_CHANNELS+NUM_CHANNELS2;
	pSSnConfig->bSkipProcessOnCRCError = 0;
	pSSnConfig->bSkipInitialDownload = 1U;
	pSSnConfig->nInitNoWait = 1;
	pSSnConfig->eProcID = PROCESSOR_SH0;
	pSSnConfig->bClearUnusedOutput = 1;

	/* copy code from schematic source file */
	memcpy(oSSnMemMap.pMemBlocks[1]->pMem, adi_ss_code_IC_1, adi_ss_code_IC_1_size*2);

	/* copy parameter from schematic source file */
	memcpy(oSSnMemMap.pMemBlocks[5]->pMem, adi_ss_param_IC_1, adi_ss_param_IC_1_size*4);


	eSSRes =  adi_ss_init(hSSnHandle, pSSnConfig);
	if(eSSRes != ADI_SS_SUCCESS)
	{
		printf("\nSSn instance initialization failed");
		exit(-1);
	}

	pSSnProperties = &oSSnProperties;

	/* Initialize SigmaStudio I/O pointers */
	for(i=0; i<NUM_CHANNELS+NUM_CHANNELS2; i++)
	{
		pSSInBuff[i] = &aSSInOutBuff[i*BLOCK_SIZE];
		pSSOutBuff[i] = pSSInBuff[i];
	}

	/* Populating hardcoded values for readback */
	for(i=0; i<2; i++)
	{
		oBkChannelInfoSharc0.nAvgMIPS[i]=10.0;
		oBkChannelInfoSharc0.nPeakMIPS[i]=20.0;
		oBkChannelInfoSharc0.nVersionInfo=0x47000000;
	}

	/*******************************************************************************/

	/* SPORT Initialization */
	if (Result==0u)
	{
		Result=Sport_Init();
	}

	/* Close TWI */
	if (Result==0u)
	{
		//Result=Stop_TWI();
	}

	while(1)
	{
#ifdef BYPASS_SS
		if(nDataAvail >= 1)
		{
			nDataAvail = 0;

			if(CallbackCount == 1)
			{
				pSportIn = &int_SP0ABuffer4[0];
				pSportOut = &int_SP0ABuffer1[0];
			}
			else if(CallbackCount == 2)
			{
				pSportIn = &int_SP0ABuffer5[0];
				pSportOut = &int_SP0ABuffer2[0];
				CallbackCount=0;
			}

		   for(i=0,j=0;i<BLOCK_SIZE*NUM_CHANNELS;i+=NUM_CHANNELS,j+=NUM_CHANNELS)
		   {
			   /*Copy ADC buffer to DAC buffer */
			   pSportOut[j]  = pSportIn[i];
			   pSportOut[j+4] = pSportIn[i];
			   pSportOut[j+1] = pSportIn[i+1];
			   pSportOut[j+5] = pSportIn[i+1];
			   pSportOut[j+2] = pSportIn[i+2];
			   pSportOut[j+6] = pSportIn[i+2];
			   pSportOut[j+3] = pSportIn[i+3];
			   pSportOut[j+7] = pSportIn[i+3];
		   }
		}
#else
		if(nDataAvail >= 1)
		{
			nDataAvail = 0;

			if(CallbackCount == 1)
			{
				pSportIn = &int_SP0ABuffer4[0];
				pSportOut = &int_SP0ABuffer1[0];
				pSportIn1 = &int_SP0ABuffer4[0];
				pSportOut1 = &int_SP0ABuffer6[0];
			}
			else if(CallbackCount == 2)
			{
				pSportIn = &int_SP0ABuffer5[0];
				pSportOut = &int_SP0ABuffer2[0];
				pSportIn1 = &int_SP0ABuffer5[0];
				pSportOut1 = &int_SP0ABuffer7[0];
				CallbackCount=0;
			}

			memcpy(nTempBuff,pSportIn,BLOCK_SIZE*NUM_CHANNELS*sizeof(int));
			memcpy(&nTempBuff[16*BLOCK_SIZE],pSportIn1,BLOCK_SIZE*NUM_CHANNELS2*sizeof(int));

			/* Fixed to float conversion and copy to SS input buffer */
			for(i=0; i<NUM_CHANNELS+NUM_CHANNELS2; i++)
			{
				//CopyFix2Float((volatile uint32_t*)&pSportIn[i], NUM_CHANNELS, pSSInBuff[i], 1, BLOCK_SIZE, 1u);
				CopyFix2Float((volatile uint32_t*)&nTempBuff[i], NUM_CHANNELS+NUM_CHANNELS2, pSSInBuff[i], 1, BLOCK_SIZE, 1u);
			}


			/* Call to the Schematic processing  */
			adi_ss_schematic_process(hSSnHandle,BLOCK_SIZE,(adi_ss_sample_t **)pSSInBuff,(adi_ss_sample_t **)pSSOutBuff,pSSnProperties);

			/* Float to fix conversion and copy back to SPORT buffer */
			for(i=0; i<NUM_CHANNELS+NUM_CHANNELS2; i++)
			{
				if(i<NUM_CHANNELS)
					CopyFloat2Fix(pSSOutBuff[i], 1, (volatile uint32_t * )&pSportOut[i], NUM_CHANNELS, BLOCK_SIZE, 0u);
				else
					CopyFloat2Fix(pSSOutBuff[i], 1, (volatile uint32_t * )&pSportOut1[i-NUM_CHANNELS], NUM_CHANNELS2, BLOCK_SIZE, 0u);
			}

			if(nDataAvail >= 1)
			{
				printf("\n Input buffer overflow detected");
				exit(-1);
			}
		}
#endif
	}
}


void adi_SMAP_Application_Callback(ADI_SS_PROC_ID eCoreID)
{
	if(eCoreID==PROCESSOR_SH0)
	{
		nSMAPReceived = 1;
	}
}



void adi_ss_comm_callback_cmd4(uint32_t *pCommPayloadBuff, int32_t  nPayloadCount, ADI_SS_SSN_HANDLE hSSn)
{
	;
}

Does the main while loop in your code serve any purpose?