integrate the export system file form ss+ to cces projects

Hi Eliam,

The error you are facing is due to a missing section (ss_app_uc_data) in the LDF file. You may have made changes to the ADSP-21569 by referring to the ADSP-21593 at the application level but might have missed updating the LDF file accordingly.



You need to include the specified section in your ADSP-21569 app.ldf file.

You can refer to this link: ADSP-2156x LibIntegration with Generated Source Files

hi VSankar

thank you very much for replying , it really resolved my issue.

now I can integrate the export system file into my cces projects, I have a further question, if I add one volume control in the schematic , how can i change the volume value in the UC host through SPI?

Hi Eliam,

The exported system files include a <SchematicName>_PARAM.h file, which indicates the addresses assigned to the parameters of a particular module. These addresses correspond to the array offsets of the parameter buffer, which you can see after generating the source files from the exported files (found in the .c file).

For example, for a Mute (SW Slew) module, the exported PARAM.h file might show:

and the generated .c file will contain the parameter buffer with the actual values placed at the specified address offsets as shown below:


You can use this mapping to correctly packetize your data frame over SPI from the Uc Host, ensuring that parameter updates are written to the correct locations in the target system.

thanks for your help.

how to resolve this warning?

hi 

  I modified the code of LibIntegrationExample of 21569 to fit the my customer board ,  I add a PCG init function to provide clock for sport 4A, 

and change the SRU like below :

when I test it in debug mode (debug as-> application with crosscore debugger) ,it works , I can probe the clock signal ,

but when I build it to .ldr file , and flash it ,after flashing done, I can't probe the clock signal.

I don't know the different between debug mode and flash mode .

Hi Eliam,

There shouldn't be any significant difference between the Debug and Flashing LDR file that would affect routing or functionality. However, out of curiosity, have you included any "printf" statements in the code during the debugging stage? If so, could you try commenting them out and testing again?

hi VSankar

I didn't add any printf statements in the current code ,besides, I want to know why can't add the "printf" statements cause I tried to add some to these printf to check the values of some variables when debug.

/*****************************************************************************
Copyright (c) 2019-2023 Analog Devices Inc. All rights reserved
This software is proprietary & confidential to Analog Devices, Inc.
and its licensors.
*****************************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <sys/platform.h>
#include <sys/adi_core.h>
#include "adi_initialize.h"
#include <services/int/adi_int.h>
#include <drivers/sport/adi_sport.h>
#include <services/spu/adi_spu.h>
#include <drivers/twi/adi_twi_2156x.h>
#include "ADAU_1962Common.h"
#include "ADAU_1979Common.h"
#include <cdef21569.h>
#include "math.h"
#include <string.h>
#include <sru21569.h>
#include "LibIntegrationExample_Core1.h"
#include "adi_ss_smap.h"
#include "adi_ss_ssn_Export_export_DiffDXESchematic_0.h"
#include "adi_ss_utility.h"
#include <services/pcg/adi_pcg.h>



/******* SigmaStudio Integration ***************/


/*Defining Backchannel info structure. Will be populated by the framework */
typedef struct ADI_SS_BACKCH_INFO
{
    float32_t    nPeakMIPS[ADI_SS_FW_MAX_PROC_BLOCKS]; /*!< Peak MIPS for all process blocks */
    float32_t    nAvgMIPS[ADI_SS_FW_MAX_PROC_BLOCKS];  /*!< Average MIPS for all process blocks */
    uint32_t     nVersionInfo;                  	   /*!< Target library API version */
    uint32_t     nSSnDownloadStatus;            	   /*!< Current download status of SSns within all process blocks*/
}ADI_SS_BACKCH_INFO;

#include "adi_ss_connection.h"
#include "adi_ss_communication.h"
#include "adi_ss_ssn.h"

/* Memory for SigmaStudio for Griffin libraries */
/* Connection and Communication Instance Mem */
#pragma align(4)
#pragma section("ss_app_data0_fast")
uint8_t adi_ss_commn_mem[ADI_SS_COMM_MEMSIZE];
#pragma align(4)
#pragma section("ss_app_data0_fast")
uint8_t adi_ss_connection_mem[ADI_SS_CONNECTION_MEMSIZE];

bool bSportCallback;
volatile uint32_t nSMAPReceived=0;

/* SMAP */
ADI_SS_MEM_SMAP oSMAPSharc0;
ADI_SS_MEM_MAP oSSnMemMap;

/* SSn Config structure */
ADI_SS_CONFIG  *pSSnConfig,oSSnConfig;

/* SSnProperties structure */
ADI_SS_SSNPROPERTIES *pSSnProperties,oSSnProperties;

/* Defining SSn Handle */
ADI_SS_SSN_HANDLE hSSnHandle;

/* Backchannel info */
ADI_SS_BACKCH_INFO 	oBkChannelInfoSharc0;

/* I/O buffer and pointers for SSn instance */
float32_t aSSInOutBuff[BLOCK_SIZE*NUM_CHANNELS];
float32_t *pSSInBuff[NUM_CHANNELS];
float32_t *pSSOutBuff[NUM_CHANNELS];

void adi_ss_comm_callback_cmd4(uint32_t  *pCommPayloadBuff,
                               int32_t   nPayloadCount,
                               ADI_SS_SSN_HANDLE hSSn);

void adi_SMAP_Application_Callback(ADI_SS_PROC_ID eCoreID);

/* Convert the audio samples generated by ADC into float format */
void    CopyFix2Float( volatile        uint32_t  *pInBuffer,
                                        uint32_t nInStride,
                       volatile        float    *pOutBuffer,
                                        uint32_t nOutStride,
                                        uint32_t nBlockSize,
                                        uint32_t nShiftFlag);

/* Convert the audio samples from float to fixed point (which can be consumed by DAC) */
uint32_t CopyFloat2Fix(volatile   float *pInBuffer,
                                        uint32_t nInStride,
                               volatile uint32_t *pOutBuffer,
                                        uint32_t nOutStride,
                                        uint32_t nBlockSize,
                                        uint32_t nShiftFlag);

/******* SigmaStudio Integration END  ***************/


/* SPORT buffers */
int32_t int_SP0ABuffer1[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer2[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer4[BLOCK_SIZE*NUM_CHANNELS];
int32_t int_SP0ABuffer5[BLOCK_SIZE*NUM_CHANNELS];

struct Config_Table
{
	short Reg_Add;
	char  Value;
};

char Config_read_DAC[28];
char Config_read_ADC[16];

/* Dev buffer for configuring ADC-DAC through TWI*/
static uint8_t devBuffer[BUFFER_SIZE];

extern void ConfigSoftSwitches_ADC_DAC(void);

extern void ConfigSoftSwitches_ADAU_Reset(void);

#if 0
struct Config_Table Config_array_DAC[28] = {
		   	    {     ADAU1962_PDN_CTRL_1,		0x00},
		   	    {     ADAU1962_PDN_CTRL_2,	    0xff},
		   	    {     ADAU1962_PDN_CTRL_3,	    0x0f},
		   	    {     ADAU1962_DAC_CTRL0,		0x01},
		   	    {     ADAU1962_DAC_CTRL1,		0x41},
		   	    {     ADAU1962_DAC_CTRL2,		0x00},
		   	    {     ADAU1962_DAC_MUTE1,	    0x0},
		   	    {     ADAU1962_DAC_MUTE2,	    0x00},
		   	    {     ADAU1962_MSTR_VOL,		0x00},
			    {     ADAU1962_DAC1_VOL,	    0x00},
			    {     ADAU1962_DAC2_VOL,		0x00},
				{     ADAU1962_DAC3_VOL,		0x00},
				{     ADAU1962_DAC4_VOL,		0x00},
				{     ADAU1962_DAC5_VOL,		0x00},
				{     ADAU1962_DAC6_VOL,		0x00},
				{     ADAU1962_DAC7_VOL,		0x00},
				{     ADAU1962_DAC8_VOL,	    0x00},
				{     ADAU1962_DAC9_VOL,		0x00},
				{     ADAU1962_DAC10_VOL,		0x00},
				{     ADAU1962_DAC11_VOL,		0x00},
				{     ADAU1962_DAC12_VOL,		0x00},
				{     ADAU1962_PAD_STRGTH,		0x00},
				{     ADAU1962_DAC_PWR1,		0xaa},
				{     ADAU1962_DAC_PWR2,		0xaa},
				{     ADAU1962_DAC_PWR3,		0xaa},
				{     ADAU1962_PDN_CTRL_2,	    0x00},
				{     ADAU1962_PDN_CTRL_3,	    0x00},
				{     ADAU1962_DAC_CTRL0,		0x18}

};
#else
struct Config_Table Config_array_DAC[28] = {
		   	    {     ADAU1962_PDN_CTRL_1,		0xa4 },
		   	    {     ADAU1962_PDN_CTRL_2,	    0xff },  //Power down DAC
		   	    {     ADAU1962_PDN_CTRL_3,	    0x0f }, //Power down DAC
		   	    {     ADAU1962_DAC_CTRL0,		0x19 },
		   	    {     ADAU1962_DAC_CTRL1,		0x63 }, // pulse mode LRCLK, MSB first //orginal value =42
		   	    {     ADAU1962_DAC_CTRL2,		0x04 },  // TDM Configuration
		   	    {     ADAU1962_DAC_MUTE1,	    0x00 },
		   	    {     ADAU1962_DAC_MUTE2,	    0x00 },
		   	    {     ADAU1962_MSTR_VOL,		0x00 },
			    {     ADAU1962_DAC1_VOL,	    0x00 } ,
			    {     ADAU1962_DAC2_VOL,		0x00 },
				{     ADAU1962_DAC3_VOL,		0x00 },
				{     ADAU1962_DAC4_VOL,		0x00 },
				{     ADAU1962_DAC5_VOL,		0x00 },
				{     ADAU1962_DAC6_VOL,		0x00 },
				{     ADAU1962_DAC7_VOL,		0x00 },
				{     ADAU1962_DAC8_VOL,	    0x00 },
				{     ADAU1962_DAC9_VOL,		0x00 },
				{     ADAU1962_DAC10_VOL,		0x00 },
				{     ADAU1962_DAC11_VOL,		0x00 },
				{     ADAU1962_DAC12_VOL,		0x00 },
				{     ADAU1962_PAD_STRGTH,		0x00 },
				{     ADAU1962_DAC_PWR1,		0xaa },
				{     ADAU1962_DAC_PWR2,		0xaa },
				{     ADAU1962_DAC_PWR3,		0xaa },
				{     ADAU1962_PDN_CTRL_2,	    0x00 },
				{     ADAU1962_PDN_CTRL_3,	    0x00 },
		   	    {     ADAU1962_DAC_CTRL0,		0x18 },
};
#endif

#if 0
struct Config_Table Config_array_ADC[16] = {

		 {ADAU1979_REG_BOOST			,	0x00},
		 {ADAU1979_REG_MICBIAS			,	0x00},
		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0x30},
		 /*{ADAU1979_REG_SAI_CTRL0		,	0x1B}, */
		 {ADAU1979_REG_SAI_CTRL0		,	0x1A},/*I2S format*/
		 {ADAU1979_REG_SAI_CTRL1		,	0x08},
		 {ADAU1979_REG_CMAP12			,	0x10},
		 {ADAU1979_REG_CMAP34			,	0x32},
		 {ADAU1979_REG_SAI_OVERTEMP		,	0xf0},
		 {ADAU1979_REG_POST_ADC_GAIN1 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN2 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN3 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN4 	,	0xA0},
		 {ADAU1979_REG_ADC_CLIP			,	0x00},
		 {ADAU1979_REG_DC_HPF_CAL		,	0x00},
		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0x3f},
		 {ADAU1979_REG_MISC_CONTROL		,	0x02}
};
#else
struct Config_Table Config_array_ADC[16] = {

		 {ADAU1979_REG_BOOST			,	0x00},
		 {ADAU1979_REG_MICBIAS			,	0x00},
 		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0xb0},//power down ADC LDO enabel
		 {ADAU1979_REG_SAI_CTRL0		,	0x5a},//TDM 48kHz
		 {ADAU1979_REG_SAI_CTRL1		,	0x08},//LRCLK pulse mode //original value =08
		 {ADAU1979_REG_CMAP12			,	0x10},
		 {ADAU1979_REG_CMAP34			,	0x32},
		 {ADAU1979_REG_SAI_OVERTEMP		,	0xf0},
		 {ADAU1979_REG_POST_ADC_GAIN1 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN1 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN3 	,	0xA0},
		 {ADAU1979_REG_POST_ADC_GAIN4 	,	0xA0},
		 {ADAU1979_REG_ADC_CLIP			,	0x00},
		 {ADAU1979_REG_DC_HPF_CAL		,	0x00},// filter off
		 {ADAU1979_REG_BLOCK_POWER_SAI	,	0xbf},//power on  ADC LDO enable
		 {ADAU1979_REG_MISC_CONTROL		,	0x02},//mute all channels
};
#endif

/* Destination PDMA lists */
ADI_PDMA_DESC_LIST iDESC_LIST_1_SP4A;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP4A ;

/* Source PDMA lists */
ADI_PDMA_DESC_LIST iSRC_LIST_1_SP0B ;
ADI_PDMA_DESC_LIST iSRC_LIST_2_SP0B ;


/* Prepares descriptors for SPORT DMA */
static void PrepareDescriptors (void);

/* Count to track the number of callBacks for SPORT transfer */
volatile uint8_t CallbackCount = 0;
volatile uint32_t TestCallbackCount = 0;
volatile uint32_t nDataAvail=0;


/* Memory required for SPORT */
static uint8_t SPORTMemory4A[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory0B[ADI_SPORT_MEMORY_SIZE];

/* SPORT Handle */
static ADI_SPORT_HANDLE hSPORTDev4ATx;//TX
static ADI_SPORT_HANDLE hSPORTDev0BRx;//RX

/* Memory required for TWI */
uint8_t TwideviceMemory[ADI_TWI_MEMORY_SIZE];

/* TWI driver handle */
static ADI_TWI_HANDLE hTwiDevice;

/* SPU handle */
static ADI_SPU_HANDLE      ghSpu;

/* Memory required for the SPU operation */
uint8_t             SpuMemory[ADI_SPU_MEMORY_SIZE];

int32_t delay;

static int32_t ADAU_1962_Pllinit(void);
static int32_t ADAU_1979_Pllinit(void);
void Switch_Configurator(void);
static int32_t ADAU_1962_init(void);
static int32_t ADAU_1979_init(void);
void SRU_Init(void);
static int32_t Sport_Init(void);
static int32_t Sport_Stop(void);
static int32_t SPU_init(void);
static void PrepareDescriptors (void);
static int32_t Init_TWI(void);
static int32_t Stop_TWI(void);
static void PCG_init(void);

static void PCG_init()
{

	ADI_PCG_CLK_INFO gClkInfoC;
			gClkInfoC.eClkInput = ADI_PCG_CLK_CLKIN0;               /* Clock Source */
			gClkInfoC.nDiv = 1;                 /* Clock Divisor */
			gClkInfoC.bExternalTrigger = false;                    /* External Trigger */


	ADI_PCG_FS_INFO gFsInfoC;
			gFsInfoC.eClkInput = ADI_PCG_FS_CLKIN0;                               /* Clock Source */
			gFsInfoC.nDiv = (gClkInfoC.nDiv)*(ADI_SPORT0A_CTL_SLEN + 1)*(16);     /* Frame Sync Divisor */
			gFsInfoC.nPulseWidth = 1;                            /* Pulse Width */
			gFsInfoC.nPhase = 511;                                /* Phase */
			gFsInfoC.bExternalTrigger = false;                                   /* External Trigger */
			gFsInfoC.eFsBypassMode = ADI_PCG_FSBYPASS_MODE_NORMAL;               /* Bypass Mode */



			adi_pcg_Init(ADI_PCG_DEV_C,&gClkInfoC,&gFsInfoC);

}

static void SPORTCallback(void        *pAppHandle,
						  uint32_t     nEvent,
						  void        *pArg
						 )
{
	int32_t i;
	int32_t j;

	ADI_SPORT_RESULT eResult;
    /* CASEOF (event type) */
    switch (nEvent)
    {
        /* CASE (buffer processed) */
        case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
        		TestCallbackCount += 1;
        		CallbackCount += 1;
        		nDataAvail += 1;
        		break;
        default:
        	 break;
    }
    /* return */
}

/*
 * Prepares descriptors for Memory DMA copy.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */

static void PrepareDescriptors (void)
{

	iDESC_LIST_1_SP4A.pStartAddr	= (int32_t *)int_SP0ABuffer1;
	iDESC_LIST_1_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_1_SP4A.XCount		= BLOCK_SIZE*NUM_CHANNELS;
	iDESC_LIST_1_SP4A.XModify		= 4;
	iDESC_LIST_1_SP4A.YCount		= 0;
	iDESC_LIST_1_SP4A.YModify		= 0;
	iDESC_LIST_1_SP4A.pNxtDscp		= &iDESC_LIST_2_SP4A;

	iDESC_LIST_2_SP4A.pStartAddr	= (int32_t *)int_SP0ABuffer2;
	iDESC_LIST_2_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_2_SP4A.XCount		= BLOCK_SIZE*NUM_CHANNELS;
	iDESC_LIST_2_SP4A.XModify		= 4;
	iDESC_LIST_2_SP4A.YCount		= 0;
	iDESC_LIST_2_SP4A.YModify		= 0;
	iDESC_LIST_2_SP4A.pNxtDscp		= &iDESC_LIST_1_SP4A;

	iSRC_LIST_1_SP0B.pStartAddr		=(int32_t *)int_SP0ABuffer4;
	iSRC_LIST_1_SP0B.Config			= ENUM_DMA_CFG_XCNT_INT ;
	iSRC_LIST_1_SP0B.XCount			= BLOCK_SIZE*NUM_CHANNELS;
	iSRC_LIST_1_SP0B.XModify		= 4;
	iSRC_LIST_1_SP0B.YCount			= 0;
	iSRC_LIST_1_SP0B.YModify		= 0;
	iSRC_LIST_1_SP0B.pNxtDscp		= &iSRC_LIST_2_SP0B;

	iSRC_LIST_2_SP0B.pStartAddr		=(int32_t *)int_SP0ABuffer5;
	iSRC_LIST_2_SP0B.Config			= ENUM_DMA_CFG_XCNT_INT;
	iSRC_LIST_2_SP0B.XCount			= BLOCK_SIZE*NUM_CHANNELS;
	iSRC_LIST_2_SP0B.XModify		= 4;
	iSRC_LIST_2_SP0B.YCount			= 0;
	iSRC_LIST_2_SP0B.YModify		= 0;
	iSRC_LIST_2_SP0B.pNxtDscp		= &iSRC_LIST_1_SP0B;
}

static int32_t Sport_Init()
{
    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

	/* Open the SPORT Device 4A */
	eResult = adi_sport_Open(SPORT_DEVICE_4A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_MC_MODE, SPORTMemory4A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/* Open the SPORT Device 0B*/
	eResult = adi_sport_Open(SPORT_DEVICE_0B,ADI_HALF_SPORT_B,ADI_SPORT_DIR_RX, ADI_SPORT_MC_MODE, SPORTMemory0B,ADI_SPORT_MEMORY_SIZE,&hSPORTDev0BRx);
	CHECK_RESULT(eResult);

	/* Configure the data,clock,frame sync and MCTL of SPORT Device 4A*/
	eResult = adi_sport_ConfigData(hSPORTDev4ATx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigClock(hSPORTDev4ATx,32,false,/*false*/ true,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigFrameSync(hSPORTDev4ATx,31,false,false,false,/*true*/ false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigMC(hSPORTDev4ATx,1u,15u,0u,true);
	CHECK_RESULT(eResult);
	eResult = adi_sport_SelectChannel(hSPORTDev4ATx,0u,15u);
	CHECK_RESULT(eResult);

	/* Configure the data,clock,frame sync and MCTL of SPORT Device 0B*/
	eResult = adi_sport_ConfigData(hSPORTDev0BRx,ADI_SPORT_DTYPE_ZERO_FILL,31,false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigClock(hSPORTDev0BRx,32,false,/*false*/ true,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigFrameSync(hSPORTDev0BRx,31,false,false,false,/*true*/ false,false,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_ConfigMC(hSPORTDev0BRx,1u,15u,0u,false);
	CHECK_RESULT(eResult);
	eResult = adi_sport_SelectChannel(hSPORTDev0BRx,0u,15u);
	CHECK_RESULT(eResult);

	/* Register SPORT Callback function */
	eResult = adi_sport_RegisterCallback(hSPORTDev0BRx,SPORTCallback,NULL);
	CHECK_RESULT(eResult);

	/* Prepare descriptors */
	PrepareDescriptors();

	/* Submit the first buffer for Rx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev0BRx,&iSRC_LIST_1_SP0B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);
	/* Submit the first buffer for Tx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev4ATx,&iDESC_LIST_1_SP4A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);

	/*Enable the Sport Device 0B */
	eResult = adi_sport_Enable(hSPORTDev0BRx,true);
	CHECK_RESULT(eResult);
	/*Enable the Sport Device 4A */
	eResult = adi_sport_Enable(hSPORTDev4ATx,true);
	CHECK_RESULT(eResult);

	return eResult;

}

static int32_t Sport_Stop(void)
{
    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

    /*Stop the DMA transfer of  Sport Device 0B */
	eResult = adi_sport_StopDMATransfer(hSPORTDev0BRx);
	CHECK_RESULT(eResult);
	/*Stop the DMA transfer of  Sport Device 4A */
	eResult = adi_sport_StopDMATransfer(hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 0B */
	eResult = adi_sport_Close(hSPORTDev0BRx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 4A */
	eResult = adi_sport_Close(hSPORTDev4ATx);
	CHECK_RESULT(eResult);

	return eResult;
}

/*
 * Prepares Switch configuration.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */
void Switch_Configurator()
{
	int32_t delay11=0xffff;


	/* Software Switch Configuration for Re-Setting ADC-DAC  */
	ConfigSoftSwitches_ADAU_Reset();

	while(delay11--)
	{
		asm("nop;");
	}

	/* Software Switch Configuration for Enabling ADC-DAC */
	ConfigSoftSwitches_ADC_DAC();

	/* wait for Codec to up */
	delay11=0xffff;
	while(delay11--)
	{
		asm("nop;");
	}
}



/*
 * Prepares SRU configuration.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */
void SRU_Init()
{
	*pREG_PADS0_DAI0_IE=0xfffff;
	*pREG_PADS0_DAI1_IE=0xfffff;

	/*SPORT 0B configuration */
    SRU(LOW,DAI0_PBEN07_I);
    SRU(DAI0_PB07_O,SPT0_BCLK_I);
    SRU(DAI0_PB08_O,SPT0_BFS_I);
    SRU(LOW,DAI0_PBEN08_I);

    SRU(LOW,DAI0_PBEN05_I);
    SRU(DAI0_PB05_O,SPT0_BD0_I);

    /*SPORT 4A configuration */

    SRU2(HIGH,DAI1_PBEN03_I);
	SRU2(PCG0_CLKC_O,DAI1_PB03_I);
	SRU2(PCG0_FSC_O,DAI1_PB04_I);
	SRU2(HIGH,DAI1_PBEN04_I);
	SRU2(PCG0_CLKC_O,SPT4_ACLK_I);
	SRU2(PCG0_FSC_O,SPT4_AFS_I);

	SRU2(SPT4_AD0_O,DAI1_PB01_I);
	SRU2(HIGH,DAI1_PBEN01_I);



}

/*
 * Prepares SPU configuration.
 *
 * Parameters
 *  None
 *
 * Returns
 *  None
 *
 */
int32_t SPU_init(void)
{
    if(adi_spu_Init(0, SpuMemory, NULL, NULL, &ghSpu) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to initialize SPU service\n");
		return FAILED;
    }

    /* Make SPORT 0A to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_4A_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT0A\n");
		return FAILED;
    }

    /* Make SPORT 0B to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_0B_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT0B\n");
		return FAILED;
    }

    return SUCCESS;
}

void Write_TWI_8bit_Reg(unsigned char Reg_ID, unsigned char Tx_Data)
{
	devBuffer[0] = Reg_ID;
	devBuffer[1] = Tx_Data;
	adi_twi_Write(hTwiDevice, devBuffer, 2u, false);
}

uint8_t Read_TWI_8bit_Reg(unsigned char Reg_ID)
{
	ADI_TWI_RESULT eResult;
	uint8_t Rx_Data;

	/* write register address */
	devBuffer[0] = Reg_ID;
	eResult = adi_twi_Write(hTwiDevice, devBuffer, 1u, true);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI write failed 0x%08X\n", eResult);
	}

	/* read register value */
	eResult = adi_twi_Read(hTwiDevice, &Rx_Data, 1u, false);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Read failed 0x%08X\n", eResult);
	}

	return Rx_Data;
}

static int32_t Init_TWI(void)
{
	ADI_TWI_RESULT eResult;

	eResult = adi_twi_Open(TWIDEVNUM, ADI_TWI_MASTER, &TwideviceMemory[0],
			   	ADI_TWI_MEMORY_SIZE, &hTwiDevice);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Open failed 0x%08X\n", eResult);
	}

	eResult = adi_twi_SetPrescale(hTwiDevice, PRESCALEVALUE);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Prescale failed 0x%08X\n", eResult);
	}

	eResult = adi_twi_SetBitRate(hTwiDevice, BITRATE);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Bitrate failed 0x%08X\n", eResult);
	}


	eResult = adi_twi_SetDutyCycle(hTwiDevice, DUTYCYCLE);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Duty cycle failed 0x%08X\n", eResult);
	}

	eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
	}

	return eResult;
}

static int32_t Stop_TWI(void)
{
	ADI_TWI_RESULT eResult;

	eResult = adi_twi_Close(hTwiDevice);
	CHECK_RESULT(eResult);

	return eResult;
}

/*****************************************************************************************************************************/

static int32_t ADAU_1962_init(void)
{
	int32_t i;
	ADAU_1962_Pllinit();
	for(i=0;i<28;i++)
	{
		/* write value */
		Write_TWI_8bit_Reg(Config_array_DAC[i].Reg_Add,Config_array_DAC[i].Value);
		Config_read_DAC[i]=Read_TWI_8bit_Reg(Config_array_DAC[i].Reg_Add);
		if(Config_array_DAC[i].Value!= Config_read_DAC[i])
		{
			DEBUG_INFORMATION("\n Configuring ADAU_1962 failed");
			return FAILED;
		}
	}

	return SUCCESS;
}

static int32_t ADAU_1962_Pllinit(void)
{
	int32_t status,delay1=0xffff;

	ADI_TWI_RESULT eResult;

   	eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR_1962);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
	}

	Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x01);
	while(delay1--)
	{
		asm("nop;");
	}

	Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x05);

	delay1=0xffff;
	while(delay1--)
	{
		asm("nop;");
	}

	Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1,0x22);
	delay1=0xffff;
	while(delay1--)
	{
		asm("nop;");
	}
	status=Read_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1);
	while(!((status & 0x4)>>2)  )
	{
		status=Read_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL1);
	}

	return eResult;
}




static int32_t ADAU_1979_init(void)
{
	int32_t i;

	ADAU_1979_Pllinit();

	for(i=0; i<16; i++)
	{
		Write_TWI_8bit_Reg(Config_array_ADC[i].Reg_Add,Config_array_ADC[i].Value);
		Config_read_ADC[i]=Read_TWI_8bit_Reg(Config_array_ADC[i].Reg_Add);
		if(Config_array_ADC[i].Value!= Config_read_ADC[i])
		{
			DEBUG_INFORMATION("\n Configuring ADAU_1979 failed");
			return FAILED;
		}
	}

	return SUCCESS;
}

static int32_t ADAU_1979_Pllinit(void)
{

	int32_t status,delay1=0xffff;

	ADI_TWI_RESULT eResult;

   	eResult = adi_twi_SetHardwareAddress(hTwiDevice, TARGETADDR_1979);
	if(eResult!=ADI_TWI_SUCCESS)
	{
		REPORT_ERROR("TWI Set Hw address failed 0x%08X\n", eResult);
	}

   	Write_TWI_8bit_Reg(ADAU1979_REG_POWER,0x01);
	Write_TWI_8bit_Reg(ADAU1979_REG_PLL,0x03);
	status=Read_TWI_8bit_Reg(ADAU1979_REG_PLL);
	while(delay1--)
	{
		asm("nop;");
	}

	while(!((status & 0x80)>>7)  )
	{
		status=Read_TWI_8bit_Reg(ADAU1979_REG_PLL);
		asm("nop;");
	}

	return eResult;

}

//#define BYPASS_SS
int32_t nTempBuff[BLOCK_SIZE*NUM_CHANNELS];
void main(int32_t argc, char *argv[])
{
	/**
	 * Initialize managed drivers and/or services that have been added to
	 * the project.
	 * @return zero on success
	 */
	uint32_t Result=0, i, j;
	ADI_SS_MEM_BLOCK oConnectionMemBlk, *pConnectionMemBlk;
	ADI_SS_CONNECTION_CONFIG oConnConfig, *pConnConfig;
	ADI_SS_CONNECTION_RESULT eConnRet = ADI_SS_CONNECTION_FAILED;
	ADI_SS_CONNECTION_HANDLE hConnHandle;

	ADI_SS_MEM_BLOCK oCommMemBlk, *pCommMemBlk;
	ADI_SS_COMM_CONFIG oCommnConfig, *pCommnConfig;
	ADI_SS_COMM_RESULT eCommRet = ADI_SS_COMM_FAILED;
	ADI_SS_COMM_HANDLE hCommHandle;

	ADI_SS_RESULT eSSRes;
	SS_SMAP_SSN_INFO    *pSSnInfo;
	ADI_SS_COMM_PROPERTIES pCommProp;
	int32_t *pSportIn, *pSportOut;

	adi_initComponents();


   /* SPU initialization */
	if (Result==0u)
	{
		Result=SPU_init();
	}

	/* Switch Configuration */
	//Switch_Configurator();

	/* SRU Configuration */
	SRU_Init();
	PCG_init();
	/* TWI Initialization */
	if (Result==0u)
	{
		//Result=Init_TWI();
	}

	/* ADAU1962 Initialization */
	if (Result==0u)
	{
		//Result=ADAU_1962_init();
	}

	/* ADAU1979 Initialization */
	if (Result==0u)
	{
		//Result=ADAU_1979_init();
	}

	/*******************************************************************************/
	/* SigmaStudio for SHARC (ADSP-SC5xx/ADSP-215xx) library integration */

	/* Connection component Initialization */
	pConnConfig = &oConnConfig;
	pConnConfig->eConnectionType = ADI_SS_CONNECTION_SPI;
	pConnConfig->nDevId = 1;
    pConnConfig->eProcID = PROCESSOR_SH0;

	pConnectionMemBlk = &oConnectionMemBlk;
	pConnectionMemBlk->nSize = ADI_SS_CONNECTION_MEMSIZE;
	pConnectionMemBlk->pMem = adi_ss_connection_mem;
	eConnRet = adi_ss_connection_Init(pConnectionMemBlk, pConnConfig, &hConnHandle);
	if(eConnRet != ADI_SS_CONNECTION_SUCCESS)
	{
        printf("\nConnection component initialization failed");
        exit(-1);
	}

	/* Communication component initialization*/
	pCommnConfig = &oCommnConfig;
	pCommnConfig->bCRCBypass = false;
	pCommnConfig->bFullPacketCRC = true;
	pCommnConfig->pfCommCmd4CallBack = (ADI_SS_COMM_CMD4_CB) adi_ss_comm_callback_cmd4;
	pCommnConfig->pfCommSMAPCallBack = (ADI_SS_COMM_SMAP_CB) adi_SMAP_Application_Callback;
	pCommnConfig->hConnectionHandle = hConnHandle;
	pCommnConfig->pMemSMap[PROCESSOR_SH0] = &oSMAPSharc0;
	pCommnConfig->pBkChnlInfo[0] = &oBkChannelInfoSharc0;

	pCommMemBlk = &oCommMemBlk;
	pCommMemBlk->nSize = ADI_SS_COMM_MEMSIZE;
	pCommMemBlk->pMem = adi_ss_commn_mem;
	eCommRet = adi_ss_comm_Init(pCommMemBlk, pCommnConfig, &hCommHandle);
	if(eCommRet != ADI_SS_COMM_SUCCESS)
	{
        printf("\nCommunication component initialization failed");
        exit(-1);
	}

	/* Wait for SMAP to be received from host */
	/*while(!nSMAPReceived)
	{

	}*/
	memcpy(&oSMAPSharc0, adi_ss_smap_DiffDXESchematic_0, adi_ss_smap_DiffDXESchematic_0_size*4);
	/* Populating Memory addresses of different blocks from SMAP */
	oSSnMemMap.nMemBlocks = 11;
	pSSnInfo = &oSMAPSharc0.oSSnInfo[0];
	for(i=0; i<oSSnMemMap.nMemBlocks; i++)
	{
		oSSnMemMap.pMemBlocks[i] = &pSSnInfo->oSSnBuff[i];
	}

	/* Create an instance of SSn */
	adi_ss_create( &hSSnHandle, &oSSnMemMap);
	if(hSSnHandle == NULL)
	{
		printf("\n SSn instance creation failed");
		exit(-1);
	}

	/* Provide SSn handle to communication component using the adi_ss_comm_SetProperties() API */
	pCommProp.haSSnHandle[PROCESSOR_SH0][0] = hSSnHandle;
	pCommProp.nNumProcBlocks = 1;
	pCommProp.nProcId = PROCESSOR_SH0;
	eCommRet = adi_ss_comm_SetProperties(hCommHandle,ADI_COMM_PROP_SSN_HANDLE,&pCommProp);
    if(eCommRet != ADI_SS_COMM_SUCCESS)
	{
		printf("\nError in Communication component");
		exit(-1);
	}

	/* Initialize the SSn instance */
	pSSnConfig = &oSSnConfig;
	pSSnConfig->hSSComm = hCommHandle;
	pSSnConfig->nBlockSize = BLOCK_SIZE ;
	pSSnConfig->nInChannels = 16;
	pSSnConfig->nOutChannels = 16;
	pSSnConfig->bSkipProcessOnCRCError = 0;
	pSSnConfig->bSkipInitialDownload = 1U;
	pSSnConfig->nInitNoWait = 1;
	pSSnConfig->eProcID = PROCESSOR_SH0;
	pSSnConfig->bClearUnusedOutput = 1;

	/* copy code from schematic source file */
	memcpy(oSSnMemMap.pMemBlocks[1]->pMem, adi_ss_code_DiffDXESchematic_0, adi_ss_code_DiffDXESchematic_0_size*2);

	/* copy parameter from schematic source file */
	memcpy(oSSnMemMap.pMemBlocks[5]->pMem, adi_ss_param_DiffDXESchematic_0, adi_ss_param_DiffDXESchematic_0_size*4);


	eSSRes =  adi_ss_init(hSSnHandle, pSSnConfig);
	if(eSSRes != ADI_SS_SUCCESS)
	{
		printf("\nSSn instance initialization failed");
		exit(-1);
	}

	pSSnProperties = &oSSnProperties;

	/* Initialize SigmaStudio I/O pointers */
	for(i=0; i<NUM_CHANNELS; i++)
	{
		pSSInBuff[i] = &aSSInOutBuff[i*BLOCK_SIZE];
		pSSOutBuff[i] = pSSInBuff[i];
	}

	/* Populating hardcoded values for readback */
	for(i=0; i<2; i++)
	{
		oBkChannelInfoSharc0.nAvgMIPS[i]=10.0;
		oBkChannelInfoSharc0.nPeakMIPS[i]=20.0;
		oBkChannelInfoSharc0.nVersionInfo=0x47000000;
	}

	/*******************************************************************************/

	/* SPORT Initialization */
	if (Result==0u)
	{
		Result=Sport_Init();
	}

	/* Close TWI */
	if (Result==0u)
	{
		//Result=Stop_TWI();
	}

	while(1)
	{
#ifdef BYPASS_SS
		if(nDataAvail >= 1)
		{
			nDataAvail = 0;

			if(CallbackCount == 1)
			{
				pSportIn = &int_SP0ABuffer4[0];
				pSportOut = &int_SP0ABuffer1[0];
			}
			else if(CallbackCount == 2)
			{
				pSportIn = &int_SP0ABuffer5[0];
				pSportOut = &int_SP0ABuffer2[0];
				CallbackCount=0;
			}

		   for(i=0,j=0;i<BLOCK_SIZE*NUM_CHANNELS;i+=NUM_CHANNELS,j+=NUM_CHANNELS)
		   {
			   /*Copy ADC buffer to DAC buffer */
			   pSportOut[j]  = pSportIn[i];
			   pSportOut[j+4] = pSportIn[i];
			   pSportOut[j+1] = pSportIn[i+1];
			   pSportOut[j+5] = pSportIn[i+1];
			   pSportOut[j+2] = pSportIn[i+2];
			   pSportOut[j+6] = pSportIn[i+2];
			   pSportOut[j+3] = pSportIn[i+3];
			   pSportOut[j+7] = pSportIn[i+3];
		   }
		}
#else
		if(nDataAvail >= 1)
		{
			nDataAvail = 0;

			if(CallbackCount == 1)
			{
				pSportIn = &int_SP0ABuffer4[0];
				pSportOut = &int_SP0ABuffer1[0];
			}
			else if(CallbackCount == 2)
			{
				pSportIn = &int_SP0ABuffer5[0];
				pSportOut = &int_SP0ABuffer2[0];
				CallbackCount=0;
			}

			memcpy(nTempBuff,pSportIn,BLOCK_SIZE*NUM_CHANNELS*sizeof(int));


			/* Fixed to float conversion and copy to SS input buffer */
			for(i=0; i<NUM_CHANNELS; i++)
			{
				//CopyFix2Float((volatile uint32_t*)&pSportIn[i], NUM_CHANNELS, pSSInBuff[i], 1, BLOCK_SIZE, 1u);
				CopyFix2Float((volatile uint32_t*)&nTempBuff[i], NUM_CHANNELS, pSSInBuff[i], 1, BLOCK_SIZE, 1u);
			}


			/* Call to the Schematic processing  */
			adi_ss_schematic_process(hSSnHandle,BLOCK_SIZE,(adi_ss_sample_t **)pSSInBuff,(adi_ss_sample_t **)pSSOutBuff,pSSnProperties);

			/* Float to fix conversion and copy back to SPORT buffer */
			for(i=0; i<NUM_CHANNELS; i++)
			{
				CopyFloat2Fix(pSSOutBuff[i], 1, (volatile uint32_t * )&pSportOut[i], NUM_CHANNELS, BLOCK_SIZE, 0u);
			}

			if(nDataAvail >= 1)
			{
				printf("\n Input buffer overflow detected");
				exit(-1);
			}
		}
#endif
	}
}


void adi_SMAP_Application_Callback(ADI_SS_PROC_ID eCoreID)
{
	if(eCoreID==PROCESSOR_SH0)
	{
		nSMAPReceived = 1;
	}
}



void adi_ss_comm_callback_cmd4(uint32_t *pCommPayloadBuff, int32_t  nPayloadCount, ADI_SS_SSN_HANDLE hSSn)
{
	;
}

you can see the code , the example is 4input and 8 output , my customer board is using tdm16 ,from sport 0B to sport 4A, 

you can see the dai0 pin5/6/7/8  and dai1 pin1/2/3/4.

 the current code is working in debug , but when I build to .ldr file , I can't probe the clock out from dai1 pin 3/4

Hi Eliam,

The last query regarding Debug and LDR file flash issue will be addressed here: the behavior is different between debug mode with flash mode - Q&A - CrossCore Embedded Studio and Add-ins - EngineerZone

Hi Eliam,

The last query regarding Debug and LDR file flash issue will be addressed here: the behavior is different between debug mode with flash mode - Q&A - CrossCore Embedded Studio and Add-ins - EngineerZone