Hi there!
We are using the parallel process mode with 3 schematics in SigmaStudioPlus (SS+) in order to optimize our layout, and we would like to understand the MIPS read that we are getting from it. The MIPS read value is reduced considerably compared to the MIPS read that we got using only 1 schematic. However when we made a measurement of the total cycles consumed by DSP we found out that it is the same compared to using only 1 schematic, showing no saving.
To make the measurement of the total cycles consumed by DSP we are toggling a GPIO output in the code routine named "SigmaStudio process loop" in the file adi_ss_app_sh0.c of the CCES DEMO project.
We are using a block size of 64 samples, 48KHz of sampling frequency and 1000 KHz for the DSP clock. Please see the attachments where are the read MIPS using 3 schematics and the GPIO toggling measurement.
READ MIPS = 263.42 (26.3%)
GPIO measurement: 840us => 840us/ 1333us = 0,63 (63%)
I understand that the value of MIPS read in the SS+ interface is for the core not for each schematic, is it correct?
Is it necessary to make any modification to the DEMO project in order to be able to use the parallel process mode in SS+?
Does this difference (26% vs 63%) make sense to you?
Please help us to understand this.
Thanks in advance.
Regards
Fernando
