SigmaStudio+ is used in dual-core mode

Hi,

Could you please share your schematic for analyzing this issue.

Thanks

Hi Chiru & Sakthivel,

Any updates for this issue?

Our schematics were so complex that one core could not run well enough. We urgently needed to use 21593's dual core. Please give us useful help, thank you.

The project I shared with you can be downloaded online, and it is work normally when using 21593 single-core, but the problem now is that dual-core does not work properly, please help fix this bug,  do you understand?? 

Sorry, I mentioned wrong processor name in previous response as ADSP-21569, The test was on ADSP-21593 with dual core processing using the modified schematic what I have shared. We are trying to simulate this issue from our end.

Hi Johnny,

Apologies for the delay in response.

We are attaching a sample ADSP21593 Dual core Lib integration project, which supports 16CH in total.

The ADSP21593 [with attached A2B transceiver AD2428] acts as an A2B sub node. For this particular example, we have taken ADI A2B Analyzer as the main node.

In this example, the target ADSP21593, by default supports 8 DAC channels and also 8 A2B upstream channels towards A2B Analyzer main node. Kindly try this at your desk, if the default application is working, you can use this and modify based on your requirement.

The attached zip file contains the target application, the Sigma Studio Plus schematic we have used to test this application and a document mentioning which all SPORTs, DAI Pins are being used here etc.

Thankyou.

ADSP21593_A2B_SubNode_16CH.zip

Hi Sankar,

Thanks for your support.

I will test it later.  I have a preliminary look, this example still uses the way of copy schematics( 

memcpy(&oSMAPSharc0, adi_ss_smap_DiffDXESchematic_0, adi_ss_smap_DiffDXESchematic_0_size*4), 

memcpy(oSSnMemMap.pMemBlocks[1]->pMem, adi_ss_code_DiffDXESchematic_0, adi_ss_code_DiffDXESchematic_0_size*2),

Hello sir,

This issue has been going on for a long time. Is there any updates?

We tried 48 In and 48 Out channels with the schematic what you shared and we could not see any issue. we shared the modified code to Pengjie over internal case please check and confirm whether you are seeing the issue on ADSP-21593 SOM eval board. 

It still has a problem, please note that this problem has nothing to do with the number of input&output channel nums, I have changed the project to 16in/16out. My test found that when the total MIPS of core1 + core2 is greater than 1000, only one input channel input signal program can run, but multiple channels input the program will crash. This phenomenon is very strange, because no matter how many channels of input signals, SS+ processing is the same, why only one channel input signal when the program can work, but 16 channels at the same time when the program crashes?

The lib integration example is to demonstrate how libarary integration can be done to run SigmaStudio schematic application. so all the SigmaStudio features not supported, since its simple BareMetal example. Please use the Demo/DemoUC example which has all the SigmaStudio features supported. 

Have you tested the Demo/DemoUC example yourself? Are there any successful cases? Is there any reason why you can make sure that it works and doesn't have the same problems as the lib integration example?
I have been asking you for a dual-core example that can download SigmaStudio+ schematics in real time, if it is based on Demo/DemoUC, do you have an example? or is there a guide on how to modify it?

There are a few questions about the Demo example:

1, I didn't find the configurations related to SRU and SPORT. Is it configured through the graphical interface of Sigmastudio+ as shown below? However, there are still some missing options here, such as selecting TDM mode and delaying the frame clock FS by several BCLK to start sampling data. Where can I set these missing options?

B. In this example, the audio clock used in the DSP is the internal PCG. If A2B is used as the input, the I2S clock of the DSP needs to be set to subordinate mode. Where can I set this?

C. Is there a more detailed explanation of the dual-core serial and parallel operation logic?  What is the correspondence between audio input/output channels and the dual-core?  Is there a flowchart available?

There are a few questions about the Demo example:

1, I didn't find the configurations related to SRU and SPORT. Is it configured through the graphical interface of Sigmastudio+ as shown below? However, there are still some missing options here, such as selecting TDM mode and delaying the frame clock FS by several BCLK to start sampling data. Where can I set these missing options?

B. In this example, the audio clock used in the DSP is the internal PCG. If A2B is used as the input, the I2S clock of the DSP needs to be set to subordinate mode. Where can I set this?

C. Is there a more detailed explanation of the dual-core serial and parallel operation logic?  What is the correspondence between audio input/output channels and the dual-core?  Is there a flowchart available?